CMPWR025 datasheet(7/7 Pages) CALMIRCO

7 / 7 page

10/18/2000

CMPWR025

CALIFORNIA MICRO DEVICES

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

4.88V

VCC2

∆: 72mV

VCC1

VOUT

M 50µs

100mV

Ch1

100mV

Ch3

100mV

1.00MS/s

Tek

4 Acqs

Ch1

@: 4.900V

Figure 4. V

CC1 rising from 0V to 5V, VCC2 = 5V.

Ch1 and Ch2: V

CC1 and VCC2, offset = 5V.

Ch3: V

OUT , offset = 5V.

CC1 Falling from 5V to 0V (VCC2 = 5V). Figure 5 shows

the primary supply V

cc1 becoming deselected during a 5V

to 0V transition. The test conditions are the same as in

Figure 4. Channel 2 switch is turned on as soon as V

cc2

and V

cc1 are about 200mV. A negative glitch appears on

cc2, when channel 2 is turned on. This has no effect on

the output voltage.

4.88V

VCC2

∆: 200mV

VCC1

VOUT

M 50µs

100mV

Ch2

100mV

Ch3

100mV

1.00MS/s

Tek

1 Acqs

Ch1

@: 4.802V

Figure 5. V

CC1 falling from 0V to 5V (VCC2 = 5V).

Ch1 and Ch2: V

CC1 and VCC2, offset = 5V.

Ch3: V

OUT , offset = 5V.

CC1 Rising (VCC2 = 5V).

Figure 6 is a bad test set-up that

shows what may happen if either power supply source

resistance R

S1 or RS2 is too large. In this example, RS2 is

increased to 0.3

Ω.

The oscillation during the power transition is caused by

the cumulated voltage change across R

S1 and RS2 being

greater than the hysteresis. The behavior is exacerbated

by:

• a high load current,

• too many parasitics on power lines, and

• noisy power sources.

To avoid such behavior, the solution is to reduce the load

or parasitic on power supply and layout, or use a more

stable power supply.

See Application Note AP-211 for more information.

4.62V

VCC2

∆: 72mV

VCC1

VOUT

M 1.00ms

100mV

Ch2

500mV

Ch3

100mV

50.0kS/s

Tek

0 Acqs

Ch3

@: 4.790V

Figure 6. V

CC1 Rising (VCC2@ = 5V).

Ch1 and Ch2: V

CC1 and VCC2@, offset = 5V.

Ch3: V

OUT, offset = 3.3V.

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