5-4

FAST AND LS TTL DATA

SN54/74LS166

TEST TABLE FOR SYNCHRONOUS INPUTS

DATA INPUT

FOR TEST

SHIFT/LOAD

OUTPUT TESTED

H

0 V

QH at tn+1

Serial

Input

4.5 V

QH at tn+8

AC WAVEFORMS

NOTE 1. tn = bit time before clocking transition

CLEAR INPUT

CLOCK INPUT

DATA

INPUT

(SEE TEST

TABLE)

OUTPUT Q

Vref

tw(clear)

tPHL

(clear-Q)

(SEE NOTE 1)

tn + 1

tn

tsu

th

tPLH

(CLK-Q)

3 V

0 V

VOH

VOL

3 V

3 V

0 V

0 V

Vref

Vref

Vref

Vref

Vref

Vref

Vref

Vref

tn

tn + 1

tsu

th

tPHL

tw(clock)

(CLK-Q)

Vref

Vref

Vref

Symbol

Parameter

Limits

Unit

Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

fMAX

Maximum Clock Frequency

25

35

MHz

VCC = 5.0 V

CL = 15 pF

tPHL

Clear to Output

19

30

ns

VCC = 5.0 V

CL = 15 pF

tPLH

tPHL

Clock to Output

23

24

35

35

ns

CC = 5.0 V

CL = 15 pF

Symbol

Parameter

Limits

Unit

Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

tW

Clock Clear Pulse Width

30

ns

VCC = 5.0 V

ts

Mode Control Setup Time

30

ns

VCC = 5.0 V

ts

Data Setup Time

20

ns

VCC = 5.0 V

th

Hold Time, Any Input

15

ns