2

®

ADS830

SPECIFICATIONS

ADS830E

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

RESOLUTION

8 Guaranteed

Bits

SPECIFIED TEMPERATURE RANGE

Ambient Air

–40 to +85

°C

ANALOG INPUT

Standard Single-Ended Input Range

2Vp-p

1.5

3.5

V

Optional Single-Ended Input Range

1Vp-p

2

3

V

Common-Mode Voltage

2.5

V

Optional Differential Input Range

2Vp-p

2

3

V

Analog Input Bias Current

1

µA

Input Impedance

1.25 || 5

M

Ω || pF

Track-Mode Input Bandwidth

–3dBFS

300

MHz

CONVERSION CHARACTERISTICS

Sample Rate

10k

60M

Samples/s

Data Latency

4

Clk Cyc

DYNAMIC CHARACTERISTICS

Differential Linearity Error (Largest Code Error)

f = 1MHz

±0.1

±1.0

LSB

f = 10MHz

±0.2

LSB

No Missing Codes

Guaranteed

Integral Nonlinearity Error, f = 1MHz

±0.3

±1.5

LSBs

f = 1MHz (–1dB input)

67

f = 10MHz (–1dB input)

54

65

dBFS

f = 9.5MHz and 9.9MHz (–7dB each tone)

–60

dBc

Signal-to-Noise Ratio (SNR)

Referred to Full Scale

f = 1MHz

49.5

dB

f = 10MHz

47

49.5

dB

Signal-to-(Noise + Distortion) (SINAD)

Referred to Full Scale

f = 1MHz

48

dB

f = 10MHz

45

48

dB

7.7

Bits

Differential Gain Error

NTSC, PAL

0.2

%

Differential Phase Error

NTSC, PAL

0.2

degrees

Output Noise

Input Tied to Common-Mode

0.2

LSBs rms

Aperture Delay Time

3ns

Aperture Jitter

1.2

ps rms

Overvoltage Recovery Time

2ns

Full-Scale Step Acquisition Time

2.5

ns

DIGITAL INPUTS

Logic Family

Convert Command

Start Conversion

100

µA

10

µA

High Level Input Voltage

+2.4

V

Low Level Input Voltage

+1.0

V

Input Capacitance

5pF

DIGITAL OUTPUTS

Logic Family

Logic Coding

VDRV = 5V

+0.1

V

+0.2

V

+4.9

V

+4.8

V

VDRV = 3V

+0.1

V

+2.8

V

Output Capacitance

5pF

ACCURACY (External Reference, 2Vp-p, Unless Otherwise Noted)

Zero Error (Referred to –FS)

at 25

°C

–2.5

±0.25

+2.5

%FS

Zero Error Drift (Referred to –FS)

±53

ppm/

°C

at 25

°C

–2.5

±0.3

+2.5

%FS

±75

ppm/

°C

Power Supply Rejection of Gain

∆ V

58

dB

Internal REFT Tolerance

Deviation from Ideal 3.0V

±10

±100

mV

Internal REFB Tolerance

Deviation from Ideal 2.0V

±10

±100

mV

External REFT Voltage Range

REFB + 0.8

3.0

V

External REFB Voltage Range

1.25

2.0

REFT – 0.8

V

Reference Input Resistance

REFT to REFB

800

k

Ω

CMOS/TTL Compatible

Rising Edge of Convert Clock

CMOS/TTL Compatible

Straight Offset Binary