FG256 datasheet(39/242 Pages) MICROSEMI

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ProASIC3L Low Power Flash FPGAs

Revision 13

2-23

Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Advanced I/O Banks

I/O Standard

Drive

Strength

Equiv.

Software

Default

Drive

Strength

Option1

Slew

Rate

VIL

VIH

VOL

VOH

IOL2 IOH2

Min.

Max.

Min.

Max.

Min.

VmA mA

3.3 V LVTTL /

3.3 V

LVCMOS

12 mA

12 mA High –0.3

0.8

3.6

0.4

2.4

3.3 V

LVCMOS Wide

Range3

100 µA

12 mA High –0.3

0.8

3.6

0.2

VCCI – 0.2 0.1 0.1

2.5 V

LVCMOS

12 mA

12 mA High –0.3

0.7

1.7

2.7

0.7

1.7

1.8 V

LVCMOS

12 mA

12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9

0.45

VCCI – 0.45 12

1.5 V

LVCMOS

12 mA

12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12

1.2 V

LVCMOS

2 mA

High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2

1.2 V

LVCMOS

Wide Range4,5

100 µA

2 mA

High –0.3 0.3 * VCCI

0.7 * VCCI 1.575

0.1

VCCI – 0.1 0.1 0.1

3.3 V PCI

Per PCI specifications

3.3 V PCI-X

Per PCI-X specifications

Notes:

1. Please note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The

configuration will NOT operate at the equivalent software.

2. Currents are measured at 85°C junction temperature.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

5. Applicable to devices operating at VCCI ≥ VCC.

6. Output slew rate can be extracted using the IBIS models.

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