AT6000(LV) Series

20

AC Timing Characteristics – 3.3V Operation

Notes:

2. CMOS buffer delays are measured from a V

3. Buffer delay is to a pad voltage of 1.5V with one output switching.

4. Max specifications are the average of mas t

5. Parameter based on characterization and simulation; not tested in production

6. Exact power calculation is available in an Atmel application note.

7. Load Definition: 1 = Load of one A or B input; 2 = Load of one L input; 3 = Constant Load; 4 = Load of 28 Clock Columns; 5

= Load of 28 Reset Columns; 6 = Tester Load of 50 pF.

Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds.

Worst case: V

Cell Function

Parameter

From

To

Load

Definition

(7)

-4

Units

Wire

(4)

t

(4)

A, B, L

A, B

1

1.8

ns

NAND

A, B, L

B

1

3.2

ns

XOR

t

A, B, L

A

1

4.0

ns

AND

t

A, B, L

B

1

3.2

ns

MUX

t

A, B

A

1

4.0

ns

LA

1

4.9

ns

D-Flip-flop

(5)

t

A, B, L

CLK

-

3.0

ns

D-Flip-flop

(5)

CLK

A, B, L

-

0

ns

D-Flip-flop

t

CLK

A

1

3.0

ns

Bus Driver

t

A

L

2

4.0

ns

Repeater

t

L, E

E

3

2.3

ns

L, E

L

2

3.0

ns

Column Clock

t

GCLK, A, ES

CLK

3

3.0

ns

Column Reset

GRES, A, EN

RES

3

3.0

ns

Clock Buffer

(5)

t

CLOCK PIN

GCLK

4

2.9

ns

Reset Buffer

(5)

t

RESET PIN

GRES

5

2.8

ns

TTL Input

(1)

I/O

A

3

1.5

ns

CMOS Input

(2)

t

I/O

A

3

2.3

ns

Fast Output

(3)

t

A

I/O PIN

6

6.0

ns

Slow Output

(3)

A

I/O PIN

6

12.0

ns

Output Disable

(5)

t

L

I/O PIN

6

5.5

ns

Fast Enable

(3)(5)

t

L

I/O PIN

6

6.5

ns

Slow Enable

(3)(5)

L

I/O PIN

6

12.5

ns

Device

Cell Types

Outputs

I

Cell

(6)

Wire, XWire, Half-adder, Flip-flop

A, B

2.3 µA/MHz

Bus

(6)

Wire, XWire, Half-adder, Flip-flop, Repeater

L

1.3 µA/MHz

Column Clock

(6)

Column Clock Driver

CLK

20 µA/MHz