15

TS68302

2117A–HIREL–11/02

Figure 7. Read Cycle Timing Diagram

Notes:

1. Setup time for asynchronous inputs IPL2-IPL0 guarantees their recognition at the next falling edge of the clock.

2. BR needs to fall at this time only to ensure being recognized at the end of the bus cycle.

3. Timing measurements are reinforced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted.

The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear

between 0.8V and 2.0V.

8

6

DATA IN

HALT / RESET

ASYNCHRONOUS

INPUTS (Note 1)

BERR/BR

(Note 2)

S0

S1

S2

S3

S4

S5

S6

FC2-FC0

A23-A1

CLKO

S7

AS

R/W

LDS-UDS

DTACK

7

15

9

11

17

18

14

12

47

28

29

47

30

13

48

31

27

47

47

47

56

32

32