1

High

Performance

EE-Based CPLD

ATF1516AS/L

Preliminary

Features

Programmable Logic Device

– 256 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 160, 192, 208-pins

– 10 ns Maximum Pin-to-Pin Delay

– Registered Operation Up To 100 MHz

– Enhanced Routing Resources

– D/T/Latch Configurable Flip Flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic utilization by burying a register within a COM output

– Automatic 3 mA Stand-By for “L” Version (Max.)

– Pin-Controlled 4 mA Stand-By Mode (Typical)

– Programmable Pin-Keeper Inputs and I/Os

– Reduced-Power Feature Per Macrocell

– 100% Tested

– Completely Reprogrammable

– 100 Program/Erase Cycles

– 20 Year Data Retention

– 2000V ESD Protection

– 200 mA Latch-Up Immunity

Enhanced Features

– Edge Controlled Power Down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

Rev. 0994A-A–01/98