35

AT89S8252

0401F–MICRO–11/03

Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms

(1)

Note:

1. AC Inputs during testing are driven at V

for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V

Float Waveforms

(1)

Note:

1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to

float when a 100 mV change from the loaded V

Serial Port Timing: Shift Register Mode Test Conditions

Symbol

Parameter

Variable Oscillator

Units

Min

Max

t

XLXL

Serial Port Clock Cycle Time

12t

CLCL

µs

t

QVXH

Output Data Setup to Clock Rising Edge

10t

ns

t

XHQX

Output Data Hold after Clock Rising Edge

2t

ns

t

XHDX

Input Data Hold after Clock Rising Edge

0

ns

t

XHDV

Clock Rising Edge to Input Data Valid

10t

ns