AT90LS2323-4SC datasheet(27/64 Pages) ATMEL

27 / 64 page

AT90S/LS2323/2343

1004D–09/01

activate the interrupt are defined in Table 9. The value on the INT01 pin is sampled

before detecting edges. If edge or toggle interrupt is selected, pulses that last longer

than one clock period will generate an interrupt. Shorter pulses are not guaranteed to

generate an interrupt. If low-level interrupt is selected, the low level must be held until

the completion of the currently executing instruction to generate an interrupt.

Sleep Modes

To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc-

tion must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode,

the MCU awakes, executes the interrupt routine and resumes execution from the

instruction following SLEEP. The contents of the register file, SRAM and I/O memory

are unaltered. If a reset occurs during Sleep mode, the MCU wakes up and executes

from the Reset vector.

Idle Mode

When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle

mode, stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt sys-

tem to continue operating. This enables the MCU to wake up from external triggered

interrupts as well as internal ones like Timer Overflow interrupt and Watchdog reset.

Power-down Mode

When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power-

down mode. In this mode, the external oscillator is stopped while the external interrupts

and the Watchdog (if enabled) continue operating. Only an external reset, a Watchdog

reset (if enabled), or an external level interrupt on INT0 can wake up the MCU.

Note that if a level-triggered interrupt is used for wake-up from Power-down mode, the

changed level must be held for some time to wake up the MCU. This makes the MCU

less sensitive to noise. The changed level is sampled twice by the Watchdog oscillator

clock and if the input has the required level during this time, the MCU will wake up. The

period of the Watchdog oscillator is 1 µs (nominal) at 5.0V and 25

°C. The frequency of

the Watchdog oscillator is voltage-dependent as shown in section “Typical Characteris-

tics” on page 49.

When waking up from Power-down mode, a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable

after having been stopped. The wake-up period is equal to the clock reset period, as

shown in Table 4 and Table 5 on page 21.

If the wake-up condition disappears before the MCU wakes up and starts to execute,

e.g., a low-level on is not held long enough, the interrupt causing the wake-up will not be

executed.

Table 9. Interrupt 0 Sense Control

ISC01

ISC00

Description

The low level of INT0 generates an interrupt request.

Reserved

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

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