AD569 datasheet(3/12 Pages) AD

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AD569

REV. A

–3–

AC PERFORMANCE CHARACTERISTICS

These characteristics are included for Design Guidance Only and are not subject to test.

+VS = +12 V; –VS = –12 V; +VREF = +5 V; –VREF = –5 V excepts where stated.

Parameter

Limit

Units

Test Conditions/Comments

Output Voltage Settling

µs max

No Load Applied

(Time to

±0.001% FS

µs typ

(DAC output measured from falling edge of LDAC.)

For FS Step)

µs max

VOUT Load = 1 kΩ, CLOAD = 1000 pF.

µs typ

(DAC output measured from falling edge of LDAC. )

Digital-to-Analog Glitch

500

nV-sec typ

Measured with VREF = 0 V. DAC registers alternatively loaded

Impulse

with input codes of 8000H and 0FFFH (worst-case

transition). Load = 1 k

Ω.

Multiplying Feedthrough

–100

dB max

+VREF = 1 V rms 10 kHz sine wave,

–VREF = 0 V

Output Noise Voltage

nV/

typ

Measured between VOUT and –VREF

Density (1 kHz-1 MHz)

TIMING CHARACTERISTICS (+VS = +12 V, –VS = –12 V, VIH = 2.4 V, VIL = 0.4 V,TMIN to TMAX)

Parameter

Limit

Units

Test Conditions/Comments

Case A

150 ns Pulse on HBE, LBE, and LDAC

THS = 140 ns min, THH = 10 ns min

tWC

120

ns min

Pulse Width

tSC

ns min

Data Setup Time

tHC

ns min

Data Hold Time

Case B

None

tWB

ns min

HBE

, LBE Pulse Width

tSB

ns min

HBE

, LBE Data Setup Time

tHB

ns min

HBE

, LBE Data Hold Time

tSCS

120

ns min

Setup Time

tHCS

ns min

Hold Time

tWD

120

ns min

LDAC

Pulse Width

Case C

None

tWB

120

ns min

HBE

, LBE Pulse Width

tSB

ns min

HBE

, LBE Data Setup Time

tHB

ns min

HBE

, LBE Data Hold Time

tSCS

120

ns min

Setup Time

tHCS

ns min

Hold Time

Figure 2a. AD569 Timing Diagram – Case B

Figure 2b. AD569 Timing Diagram – Case C

Figure 1. AD569 Timing Diagram – Case A

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