TSL3301CL

102 × 1 LINEAR OPTICAL SENSOR ARRAY

WITH ANALOG-TO-DIGITAL CONVERTER

TAOS141 − JULY 2011

3

The LUMENOLOGY

r Company

r

r

Copyright

E 2011, TAOS Inc.

www.taosinc.com

Table 1. Gain Settings and Results

GAIN CODE

RELATIVE GAIN

% INCREASE

GAIN CODE

RELATIVE GAIN

% INCREASE

0

1

16

1.52

3.23

1

1.02

2.17

17

1.57

3.33

2

1.05

2.22

18

1.62

3.45

3

1.07

2.27

19

1.68

3.57

4

1.09

2.33

20

1.74

3.70

5

1.12

2.38

21

1.81

3.85

6

1.15

2.44

22

1.88

4.00

7

1.18

2.50

23

1.96

4.17

8

1.21

2.56

24

2.05

4.35

9

1.24

2.63

25

2.14

4.55

10

1.27

2.70

26

2.24

4.76

11

1.31

2.78

27

2.35

5.00

12

1.34

2.86

28

2.48

5.26

13

1.38

2.94

29

2.61

5.56

14

1.43

3.03

30

2.77

5.88

15

1.47

3.13

31

2.94

6.25

Serial Interface

The serial interface follows a USART format, with start bit, 8 data bits, and one or more stop bits. Data is clocked

in synchronously on the rising edge of SCLK and clocked out on the falling edge of SCLK. Stop bits are not

required on the input. When clocking data out continuously (i.e., reading out pixels) there will be one stop bit

between data words.

The receive and transmit state machines are independent, which means commands can be issued while

reading data. This feature allows starting new integration cycles while reading data. Note that this allows

undefined conditions so care must be taken not to issue commands that will cause outputs (such as register

read) while reading out data. For instance, issuing a register read command while reading out image data will

result in garbage out. Likewise, it is possible to change offset and gain registers during a readout, which can

give unpredictable results.

It is not necessary to have a continuously active clock, but a minimum of 5 clocks after the stop bit is required

after any command has been issued to ensure that the corresponding internal logic actions have been

completed. When reading register contents, there will be a 4-clock delay from the completion of the REGRead

command before the register contents are output (see Figure 5). When reading out pixel values, there will be

a 44-clock delay from completion of the READPixel command until the first pixel data is output. When starting

integration (STARTInt), it is necessary to have 22 clocks to complete the pixel reset cycle (see Imaging below).