TSL2572

LIGHT-TO-DIGITAL CONVERTER

TAOS132 − MARCH 2012

17

The LUMENOLOGY

r Company

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r

Copyright

E 2012, TAOS Inc.

www.taosinc.com

Status Register (0x13)

The Status Register provides the internal status of the device. This register is read only.

Table 11. Status Register

6

75

4

AVALID

2

31

0

STATUS

Reserved

AINT

Reset

0x00

Reserved

FIELD

BIT

DESCRIPTION

Reserved

7:5

Reserved. Bits read as 0.

AINT

4

ALS Interrupt. Indicates that the device is asserting an ALS interrupt.

Reserved

3:1

Reserved. Bits read as 0.

AVALID

0

ALS Valid. Indicates that the ALS channels have completed an integration cycle after AEN has been

asserted.

ADC Channel Data Registers (0x14 − 0x17)

should be used with auto increment protocol bits set in the command register. With this operation, when the

lower byte register is read, the upper eight bits are stored in a shadow register, which is read by a subsequent

read to the upper byte. The upper register will read the correct value even if additional ADC integration cycles

end between the reading of the lower and upper registers.

Table 12. ADC Channel Data Registers

REGISTER

ADDRESS

BITS

DESCRIPTION

C0DATA

0x14

7:0

ALS CH0 data low byte

C0DATAH

0x15

7:0

ALS CH0 data high byte

C1DATA

0x16

7:0

ALS CH1 data low byte

C1DATAH

0x17

7:0

ALS CH1 data high byte