TSL2568, TSL2569

LIGHT-TO-DIGITAL CONVERTER

TAOS091D − DECEMBER 2008

12

r

r

Copyright

E 2008, TAOS Inc.

The LUMENOLOGY

r Company

www.taosinc.com

Command Register

The command register specifies the address of the target register for subsequent read and write operations.

The Send Byte protocol is used to configure the COMMAND register. The command register contains eight bits

as described in Table 3. The command register defaults to 00h at power on.

Table 3. Command Register

6

75

4

ADDRESS

2

31

0

0

00

0

0

00

0

Reset Value:

COMMAND

CLEAR

CMD

WORD

BLOCK

FIELD

BIT

DESCRIPTION

CMD

7

Select command register. Must write as 1.

CLEAR

6

Interrupt clear. Clears any pending interrupt. This bit is a write-one-to-clear bit. It is self clearing.

WORD

5

SMB Write/Read Word Protocol. 1 indicates that this SMB transaction is using either the SMB Write Word or

Read Word protocol.

BLOCK

4

Block Write/Read Protocol. 1 indicates that this transaction is using either the Block Write or the Block Read

protocol. See Note below.

ADDRESS

3:0

Register Address. This field selects the specific control or status register for following write and read

commands according to Table 2.

SMBus read/write protocol requires a Byte Count. All four ADC Channel Data Registers (Ch through Fh) can be read simultaneously in

a single SMBus transaction. This is the only 32-bit data block supported by the TSL2568 SMBus protocol. The BLOCK bit must be set

to 1, and a read condition should be initiated with a COMMAND CODE of 9Bh. By using a COMMAND CODE of 9Bh during an SMBus

Block Read Protocol, the TSL2568 device will automatically insert the appropriate Byte Count (Byte Count = 4) as illustrated in Figure 15.

A write condition should not be used in conjunction with the Bh register.

Control Register (0h)

The CONTROL register contains two bits and is primarily used to power the TSL256x device up and down as

shown in Table 4.

Table 4. Control Register

6

75

4

POWER

2

31

0

0

00

0

0

00

0

Reset Value:

CONTROL

Resv

Resv

Resv

Resv

Resv

Resv

0h

FIELD

BIT

DESCRIPTION

Resv

7:2

Reserved. Write as 0.

POWER

1:0

Power up/power down. By writing a 03h to this register, the device is powered up. By writing a 00h to this

register, the device is powered down.

NOTE: If a value of 03h is written, the value returned during a read cycle will be 03h. This feature can be

used to verify that the device is communicating properly.