TSL2014 datasheet(3/11 Pages) AMSCO

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TSL2014

896 y 1 LINEAR SENSOR ARRAY

TAOS040C − AUGUST 2011

E 2011, TAOS Inc.

The LUMENOLOGY

r Company

www.taosinc.com

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AO1

Analog output of section 1.

AO2

Analog output of section 2.

CLK

Clock. The clock controls the charge transfer, pixel output and reset.

GND

Ground (substrate). All voltages are referenced to GND.

SI1

Serial input (section 1). SI1 defines the start of the data-out sequence.

SI2

Serial input (section 2). SI2 defines the start of the data-out sequence.

SO1

Serial output (section 1). SO1 signals the end of the data out sequence and provides a signal to drive the input

of section 2 (SI2) in serial mode.

SO2

Serial output (section 2). SO2 signals the end of the data out sequence and provides a signal to drive the input

of another device for cascading.

VDD

1, 10

Supply voltage. Supply voltage for both analog and digital circuits.

Detailed Description

The sensor consists of 896 photodiodes arranged in a linear array. Light energy impinging on a photodiode

generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During

the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.

The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration

time. The integration time is the interval between two consecutive output periods.

The output and reset of the integrators is controlled by two 448-bit shift registers and reset logic. A 448-pixel

output cycle is initiated by clocking in a logic 1 into the SI input of a section for one positive going clock edge

(see Figures1 and 2) †. The two 448-pixel sections may be operated independently using a single clock input

or connected in series to form a 896-pixel array. Each section has an independent output (AO), which may be

connected together for the 896-pixel function.

When operating in the 896-pixel mode, as the SI pulse is clocked through the 896-bit shift register, the charge

on the sampling capacitor of each pixel is sequentially connected to a charge-coupled output amplifier that

generates a voltage output, AO. When the bit position goes low, the pixel integrator is reset. On the 897th clock

rising edge, the SI pulse is clocked out of the shift register (S2) and the output assumes a high-impedance state.

Note that this 897th clock pulse is required to terminate the output of the 896th pixel and return the internal logic

to a known state. A subsequent SI pulse can be presented as early as the 898th clock pulse, thereby initiating

another pixel output cycle.

The voltage developed at analog output (AO) is given by:

Vout = Vdrk + (Re) (Ee) (tint)

where:

Vout

is the analog output voltage for white condition

Vdrk

is the analog output voltage for dark condition

is the device responsivity for a given wavelength of light given in V/(

μJ/cm2)

is the incident irradiance in

μW/cm2

tint

is integration time in seconds

AO is driven by a source follower that requires an external pulldown resistor (330-

Ω typical). The output is

nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device

is not in the output phase, AO is in a high impedance state.

A 0.1

μF bypass capacitor should be connected between VDD and ground as close as possible to the device.

† For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.

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