AS8501 - Data Sheet

austriamicrosystems

Revision 1.1, 04-April-06

www.austriamicrosystems.com

Page 25 of 40

7.5.8

THR alarm (Wake-up) threshold register ( 17 bits )

Nr.

MR16 MR15 MR14 MR13 MR12

MR11 … MR1

MR0

NOTE

0

A/B

s

Msb

lsb

default

0

0

1

0

0

Notes:

1) _

All measurements are performed in channel A therefore MR16 must be set to zero. When channel B is selected

no interrupt will be generated.

- The signed value is used. For positive THR values the ASSP will initiate an interrupt whenever the measured

value is bigger than the THR value. For negtive THR values the interrupt will be generated for a negative

result with an absolute value bigger than the absolute value of the THR register.

7.5.9

MSR measurement result register ( 18 bits )

Nr.

MR17

MR16

MR15

MR14

MR13

MR12

MR11 … MR1

MR0

NOTE

Overflow/un

derflow

A/B

S

msb

lsb

1)

Notes:

1)

- Result word length is 16 bits because of calibration accuracy

and to maintain all possible resolutions ( different setting ).

- A/B bit signifies which measurement was performed: the one defined in CRA or CRB:

MR16=0 -> A

MR16=1 -> B

- Overflow/underflow bit is set whenever the result after multiplication by calibration

constant is bigger than 32767 or smaller than –32767.

In Wake-up or Alarm mode the overflow/underflow always sets INTN signal to LO.

8

Digital interface description

The digital interface of the AS8501 consists of two input pins (CLK and SCLK) and two I/O pins (INTN and SDAT). The SCLK and SDAT pins

are used as universal serial data interface (SDI). SDI operates only if external clock signal (CLK) is running.

8.1

CLK

In all operating modes except the Wake-up mode this pin must be connected to 8 MHz clock signal. In the Wake-up mode (MWU) the CLK pin

must be connected to logic HI or float.

8.2

INTN

The INTN pin is used to signal various conditions to the microcontroller, depending on the operating mode.

application modes of the INTN pin

Mode

Signal

Direction

Purpose

Note

0

Load clock (internal)

Output

Indicates progress of the Zener-Zap load process

1)

1, 2,7

SDI clock disable

Output

Signals new result and suggests when to disable SCLK in

high-precision measurement phase

2)

3

idle / wake-up not

Output

Signals the wake-up condition

4

idle / alarm not

Output

Signals the alarm condition

5

PW1

Input

Shows the programming pulse width

6,8,9

Logic ‘0’

Output

No purpose

10

t12

Output

Test mode

10

t18

Output

Test mode

Notes:

1)

188 clock pulses are generated from the internal oscillator source during the loading time.

2)

In measurement modes (MMS and MMD) the INTN pin is used to synchronize the SDI bus operations (See Fig. 9).

The trailing edge of INTN signals the start of a new measurement.