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Revision 1.18

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AS7620

Datasheet - D e t a i l e d D e s c r i p t i o n

8.7 Power Fail / Power Good

are provided outside to inform about early input power fail (active low) and output within regulation. Figure 19 illustrates the typical connection for

VEPF. During start up, PF is initially low. By selecting R3, R4, R5 and R6, it is possible to set the desired input voltage threshold above which the

Figure 19. Open-Drain Output Stage for Comparator

Table 5 provides the resistors values covering all the standard input BUS. The resistors values are 1% commercial values. It is mandatory to use

the correct resistors values to guarantee the respect of maximum absolute voltages at EPF and PF pin. VDD has been considered 3.3V.

Otherwise EPF pin should be shorted to GND and PF left floating.

Terminology:

VRST: Reset voltage for the EPF. It is 90% of the Input BUS voltage.

VTRIP: Trip voltage for the EPF. It is 80% of the Input BUS voltage.

8.8 Thermal Protection

The internal junction temperature is continuously monitored. If it reaches 150ºC (min), the PMOS is turned off. The device can switch again if the

temperature is decreased by at least 10ºC. If the over-temperature persists, the device will be shut down again resulting in a hiccup mode for the

output power.

Table 5. EPF Network Selection with Different Input BUS

VRST (V)

VTRIP (V)

R3 (K

Ω)

R4 (K

Ω)

R5 (K

Ω)

R6 (K

Ω)

5

4.5

4

365

143

1740

1370

6

5.4

4.8

464

143

1870

1430

9

8.1

7.2

768

140

2050

1580

12

10.8

9.6

1070

140

2100

1650

15

13.5

12

1370

140

2150

1690

20

18

16

1870

140

2210

1740

24

21.6

19.2

2260

140

2260

1740

28

25.3

22.5

2670

140

2260

1740

VDDH

3.6…32V

VDD

1.2…3.6

Power Fail

R6

R3

R4

R5

INV

-

+