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AS5115

Datasheet - Detailed Descr i pti on

7.9 OTP Programming and Verification

Figure 9. OTP Programming Connection

Note: The maximum capacitive load at PROG in normal operation should be less than 20pF. However, during programming the capacitors

C1+C2 are needed to buffer the programming voltage during current spikes, but they must be removed for normal operation. To

(special case setup), if the capacitors can not be removed at final assembly.

During programming the OTP, the diode ensures that no current is flowing from PROG (8V - 8.5V) to VDD (5V).

In the standard case (see Figure 9), the verification of a correct OTP readout can be done by analog readback of the OTP register.

As long as the PROG pin is accessible it is recommended to use standard setup. In case the PROG pin is not accessible at final

assembly, the special setup is recommended.

VDD

VSS

Micro

Controller

AS5130

100n

VSS

+5V

VDD

CS

VDD

DCLK

DIO

PROG

VSS

+

10µF 100n

8.0 - 8.5V

I/O

Output

Output

PROG

GND

C1

C2

100nF

10µF

PROM Cell

maximum

parasitic cable

inductance

L<50nH

Standard Case

PROG

GND

C1

C2

100nF

10µF

PROM Cell

L<50nH

Special Case

Remove for normal operation