AS3911 datasheet(39/149 Pages) AMSCO

39 / 149 page

ams Datasheet, Confidential: 2013-Oct [2-03]

AS3911 – 39

Appl icatio n I n f o rm a t i o n

Figure 22 provides information on the SPI operation modes.

Reading and writing of registers is possible in any AS3911

operation mode. FIFO operations are possible in case en (bit 7

of the Operation Control Register) is set and Xtal oscillator

frequency is stable.

Figure 22:

SPI Operation Modes

Writing of Data to Addressable Registers (Write

Mode)

Following figures show cases of writing a single byte and

writing multiple bytes with auto-incrementing address. After

the SPI operation mode bits, the address of register to be

written is provided. Then one or more data bytes are transferred

from the SPI, always from the MSB to the LSB. The data byte is

written in register on falling edge of its last clock. In case the

communication is terminated by putting /SS high before a

packet of 8 bits composing one byte is sent, writing of this

address does not exist or it is a read only register no write is

performed.

MODE

MODE Pattern (communication bits)

MODE Related Data

MODE

Trailer

A5A4

A3A2A1A0

Data byte (or more bytes in case

of auto-incrementing)

Data byte (or more bytes in case

of auto-incrementing)

FIFO Load

1000

0000

One or more bytes of FIFO data

FIFO Read

1011

1111

One or more bytes of FIFO data

Direct Command

Mode

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