www.austriamicrosystems.com/AS3648

1.5-4

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AS3648

Datasheet, Confidential - D e ta i l e d D e s c r i p t i o n

Figure 25. AS3648 flash duration defined by flash_timeout, starting flash with STROBE rising edge

Figure 26. AS3648 flash duration and start defined by STROBE, limited by flash_timeout; timer not expired

Figure 27. AS3648 flash duration and start defined by STROBE, limited by flash_timeout; timer expired

The AS3648 supports the I

device receiving data as a receiver. The device that controls the message is called a master. The devices that are

controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls the

bus access, and generates the START and STOP conditions must control the bus. The AS3648 operates as a slave on

the I

maximum clock rate) are defined. The AS3648 works in both modes. Connections to the bus are made through the

open-drain I/O lines SDA and SCL.

The following bus protocol has been defined (Figure 28):









  

  

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