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AS3643 датащи(PDF) 12 Page - ams AG |
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AS3643 датащи(HTML) 12 Page - ams AG |
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12 / 34 page ![]() www.austriamicrosystems.com/AS3643 1.5-4 11 - 33 AS3643 Datasheet, Confidential - D e ta i l e d D e s c r i p t i o n 4MHz/1MHz Operating Mode Switching If freq_switch_on (see page 26)=1 and in flash and assist light mode (indicator mode or low current mode using PWM mode -see mode_setting (page 24) - always will use pulseskip) if led_current>=40h , the DCDC converter always oper- ates in PWM mode (exception: PFM mode is allowed during startup) to reduce EMI in EMI sensitive systems. For flash and assist light mode and high duty cycles close to 100% on-time (maximum duty cycle) of the PMOS, the DCDC con- verter can switch into a 1MHz operating mode and maximum duty cycle to improve efficiency for this load condition 3. The DCDC converter returns back to its normal 4MHz operating frequency when load or supply conditions change. Due to this switching between two fixed frequencies the noise spectrum of the system is exactly defined and predict- able. If improved efficiency is required, the fixed switching between 1MHz / 4MHz can be disabled by freq_switch_on (see page 26)=0. In this case pulseskip will be used. The internal circuit for switching between these two frequencies is shown in Figure 17: Figure 17. Internal circuit of 4MHz/1Mhz selection Note: For simplicity Figure 17 shows only a single current sink. Protection and Fault Detection Functions The protection functions protect the AS3643 and the LED(s) against physical damage. In most cases a Fault register bit is set, which can be readout by the I 2C interface. The fault bits are automatically cleared by a I2C readout of the fault register. Additionally the DCDC is stopped and the current sinks are disabled 4 by resetting out_on=0, mode_setting=00 and ext_torch_on=00. Overvoltage Protection In case of no or a broken LED(s) at the pin LED_OUT1/2 and an enabled DCDC converter, the voltage on VOUT1/2 rises until it reaches VVOUTMAX (overvoltage condition) and the voltage across the current source is below low_vds 5., the DCDC converter is stopped, the current sources are disabled and the bit fault_ovp (see page 25) is set 6. 3. Efficiency compared to a 4MHz only DCDC converter forced to operate with minimum duty cycle. 4. Applies for all faults except TXMASK event occurred 5. If overvoltage is reached, but none of the low_vds comparator(s) triggers, VOUT1/2 is still regulated below VVOUTMAX. 6. In constant voltage mode (5V generation, register bit const_v_mode=1) this fault is disabled. ! " " &% '( )) * + ,- $. !'/ #0 $. ! #0 $. / %!'/ $. 1 $2 #0 34526 AS3643 |
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