AS3517 datasheet(75/94 Pages) AMSCO

75 / 94 page

AS3517 V17

Data Sheet, Confidential

www.austriamicrosystems.com

Table 75 PMU CVDD3 Register

Name

Base

Default

PMU CVDD3

2-wire serial

0x00

CVDD3 DC/DC Buck Regulator Control Register

Offset: 17h-5

This is an extended register and needs to be enabled by writing 101bto Reg. 18h first.

This register is reset at a DVDD-POR.

Bit

Bit Name

Default

Access

Bit Description

SKIP_OFF_CVDD3

R/W

Disables pulse skip mode

0: 170mA current force / pulse skip mode enabled

1: current force / pulse skip mode disabled (only ON without

load)

PROG_CVDD3

R/W

Enables settings either selected by external pin (VPRGx) or

settings stored in the 17h-5 register

0: VPRGx pins controlled

1: Register controlled

5:0

VSEL_CVDD3

00000

R/W

The voltage select bits set the DC/DC output voltage level and

power the DC/DC converter down.

00000: DC/DC powered down

01h until 38h in 50mV steps

CVDD2=0.6V+VSEL_CVDD1*50mV

(0.65V until 3.4V)

38h until 3Fh = 3.4V (no change)

Table 76 PMU Hibernate Register

Name

Base

Default

PMU Hibernate

2-wire serial

00h

PMU Hibernation Control Register (PVDD1/2, CVDD1/2/3, VLED)

Offset: 17h-6

Hibernation is started when writing to this register.

This is an extended register and needs to be enabled by writing 110b to Reg. 18h first.

This register is reset at a DVDD-POR.

Bit

Bit Name

Default

Access

Bit Description

n/a

KEEP_PVDD2

R/W

Keeps the programmed PVDD2 level during hibernation

0: power down PVDD2

1: keep PVDD2

KEEP_PVDD1

R/W

Keeps the programmed PVDD1 level during hibernation

0: power down PVDD1

1: keep PVDD1

KEEP_VLED

R/W

Keeps the 15V DC/DC step-up for backlight switched on

0: power down CVDD1

1: keep CVDD1

KEEP_VBUS

R/W

Keeps the programmed VBUS level during hibernation

0: power down CVDD2

1: keep CVDD2

KEEP_CVDD3

R/W

Keeps the programmed CVDD3 level during hibernation

0: power down CVDD3

1: keep CVDD3

KEEP_CVDD2

R/W

Keeps the programmed CVDD2 level during hibernation

0: power down CVDD2

1: keep CVDD2

KEEP_CVDD1

R/W

Keeps the programmed CVDD1 level during hibernation

0: power down CVDD1

1: keep CVDD1

Revision 1v3

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