PIC17C44 datasheet(46/241 Pages) MICROCHIP

46 / 241 page

PIC17C4X

DS30412C-page 46

7.2

Table Writes to External Memory

Table writes to external memory are always two-cycle

instructions. The second cycle writes the data to the

external memory location. The sequence of events for

an external memory write are the same for an internal

write.

Note:

If an interrupt is pending or occurs during

the TABLWT, the two cycle table write

completes. The RA0/INT, TMR0, or T0CKI

interrupt ﬂag is automatically cleared or

the

pending

peripheral

interrupt

acknowledged.

7.2.2

TABLE WRITE CODE

The “i” operand of the TABLWT instruction can specify

that the value in the 16-bit TBLPTR register is auto-

matically

incremented

for

the

write.

Example 7-1, the TBLPTR register is not automatically

incremented.

EXAMPLE 7-1:

TABLE WRITE

CLRWDT

; Clear WDT

MOVLW

HIGH (TBL_ADDR) ; Load the Table

MOVWF

TBLPTRH

;

address

MOVLW

LOW (TBL_ADDR)

;

MOVWF

TBLPTRL

;

MOVLW

HIGH (DATA)

; Load HI byte

TLWT

1, WREG

;

in TABLATCH

MOVLW

LOW (DATA)

; Load LO byte

TABLWT

0,0,WREG

;

in TABLATCH

;

and write to

;

program memory

;

(Ext. SRAM)

FIGURE 7-5:

TABLWT WRITE TIMING (EXTERNAL MEMORY)

Q1 Q2 Q3 Q4

AD15:AD0

Instruction

fetched

Instruction

executed

ALE

TABLWT

INST (PC+1)

INST (PC-1)

TABLWT cycle1

TABLWT cycle2

INST (PC+2)

Data write cycle

'1'

PC+1

TBL

PC+2

Data out

INST (PC+1)

Note:

If external write GLINTD = '1', Enable bit = '1', '1'

→ Flag bit, Do table write. The highest pending interrupt is cleared.

PIC17C44 датащи(PDF) 46 Page - Microchip Technology

PIC17C44 датащи(HTML) 46 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL