EPC4 datasheet(29/36 Pages) ALTERA

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Timing Information

Page 29

Enhanced Configuration (EPC) Devices Datasheet

January 2012

Altera Corporation

Timing Information

Figure 7 shows the configuration timing waveform when you are using an EPC

device.

Table 14 lists the timing parameters when you are using the EPC devices.

tJPXZ

JTAG port valid output to high impedance

—

tJSSU

Capture register setup time

—

tJSH

Capture register hold time

—

tJSCO

Update register clock to output

—

tJSZX

Update register high-impedance to valid output

—

tJSXZ

Update register valid output to high impedance

—

Table 13. JTAG Timing Parameters and Values (Part 2 of 2)

Symbol

Parameter

Min

Max

Unit

Figure 7. Configuration Timing Waveform Using an EPC Device

Notes to Figure 7:

(1) The EPC device drives DCLK low after configuration.

(2) The EPC device drives DATA[] high after configuration.

Byte0

Byte1

Byte2 Byte3

Byten

Tri-State

User Mode

(2)

tOEZX

tPOR

tCH

tCL

tDSU

tCO

tDH

Tri-State

OE/nSTATUS

nCS/CONF_DONE

DCLK

DATA[7..0]

User I/O

INIT_DONE

nINIT_CONF or VCC/nCONFIG

Table 14. EPC Device Configuration Parameters (Part 1 of 2)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

fDCLK

DCLK

frequency

40% duty cycle

—

66.7

MHz

tDCLK

DCLK

period

—

tHC

DCLK

duty cycle high time

40% duty cycle

—

tLC

DCLK

duty cycle low time

40% duty cycle

—

tCE

to first DCLK delay

—

tOE

to first DATA available

—

tOH

DCLK

rising edge to DATA change

—

(1)

——

tCF (2)

assert to DCLK disable delay

—

277

—

tDF (2)

assert to DATA disable delay

—

277

—

tRE (3)

DCLK

rising edge to OE

—60

—

tLOE

assert time to assure reset

—

fECLK

EXCLK

input frequency

40% duty cycle

—

100

MHz

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