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AS1339

Datasheet - A p p l i c a t i o n I n f o r m a t i o n

Layout Considerations

Please carefully observe that large peak currents of up to 1.1A and high switching frequencies will make the PCB lay-

out a very important part of the system performance and compliance. A proper PCB design will minimize electro mag-

netic interference (EMI) as well as voltage gradients in the ground plane, which both can result in application

instabilities. Please closely follow the guidelines as mentioned below.

- Keep the power traces as short and wide as possible (IN1A, IN1B, IN2, LX, PAA, PAB, PGND)

- Place all capacitors as close as possible to the pins of the device

- Avoid voltage gradients in the ground plane

Please note the following PCB layout considerations shown in Figure 54:

- The negative terminals of COUT and CIN1/CIN2 are kept as close as possible to each other. It is recommended

to connect these terminals directly to PGND at a star point.

- The current path between pins IN1A/IN1B (C3/C4) and pin PGND (A4) via CIN1 is routed very short

- The current path between pins PAB/PAA (D3/D4) and pin PGND (A4) via COUT is routed very short

- The connection between LX (B4) and pins PAB/PAA (D3/D4) via the coil (L) is routed very short

- To keep the cross-coupling between the LDOs and DC/DC minimized, in regard to supply ripple and noise induc-

tion, the IN1 and IN2 path are separated. Both power inputs should be connected at a star point directly at the

main supply

- To prevent voltage gradients between AGND (A2) and PGND (A4), these pins are connected via a short, low

ohmic, trace to each other.

Figure 54. Layout for Space Limited Applications