64GA106 datasheet(196/330 Pages) MICROCHIP

196 / 330 page

PIC24FJ256GA110 FAMILY

DS39905E-page 196

 2010 Microchip Technology Inc.

UxMODE: UARTx MODE REGISTER

R/W-0

U-0

R/W-0

U-0

R/W-0

UARTEN(1)

—

USIDL

IREN(2)

RTSMD

—

UEN1

UEN0

bit 15

bit 8

R/C-0, HC

R/W-0

R/W-0, HC

R/W-0

WAKE

LPBACK

ABAUD

RXINV

BRGH

PDSEL1

PDSEL0

STSEL

bit 7

bit 0

Legend:

C = Clearable bit

HC = Hardware Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

UARTEN:

UARTx Enable bit(1)

= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>

= UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is

minimal

bit 14

Unimplemented:

Read as ‘0’

bit 13

USIDL:

Stop in Idle Mode bit

= Discontinue module operation when the device enters Idle mode

= Continue module operation in Idle mode

bit 12

IREN:

IrDA® Encoder and Decoder Enable bit(2)

= IrDA encoder and decoder enabled

= IrDA encoder and decoder disabled

bit 11

RTSMD:

Mode Selection for UxRTS Pin bit

=UxRTS pin in Simplex mode

=UxRTS pin in Flow Control mode

bit 10

Unimplemented:

Read as ‘0’

bit 9-8

UEN<1:0>:

UARTx Enable bits

= UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by port latches

= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches

= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by port

latches

bit 7

WAKE:

Wake-up on Start Bit Detect During Sleep Mode Enable bit

= UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared in

hardware on following rising edge

= No wake-up enabled

bit 6

LPBACK:

UARTx Loopback Mode Select bit

= Enable Loopback mode

= Loopback mode is disabled

bit 5

ABAUD:

Auto-Baud Enable bit

= Enable baud rate measurement on the next character – requires reception of a Sync field (55h);

cleared in hardware upon completion

= Baud rate measurement disabled or completed

Note 1:

If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See

Section 10.4 “Peripheral Pin Select”

for more information.

This feature is only available for the 16x BRG mode (BRGH = 0).

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