64GA106 datasheet(172/330 Pages) MICROCHIP

172 / 330 page

PIC24FJ256GA110 FAMILY

DS39905E-page 172

 2010 Microchip Technology Inc.

OCxCON1: OUTPUT COMPARE x CONTROL 1 REGISTER

U-0

R/W-0

U-0

—

OCSIDL

OCTSEL2

OCTSEL1

OCTSEL0

—

bit 15

bit 8

R/W-0

U-0

R/W-0, HCS

R/W-0

ENFLT0

—

OCFLT0

TRIGMODE

OCM2(1)

OCM1(1)

OCM0(1)

bit 7

bit 0

Legend:

HCS = Hardware Clearable/Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-14

Unimplemented:

Read as ‘0’

bit 13

OCSIDL:

Stop Output Compare x in Idle Mode Control bit

= Output Compare x halts in CPU Idle mode

= Output Compare x continues to operate in CPU Idle mode

bit 12-10

OCTSEL<2:0>:

Output Compare x Timer Select bits

111

= Peripheral Clock (FCY)

110

= Reserved

101

= Reserved

100

= Timer1

011

= Timer5

010

= Timer4

001

= Timer3

000

= Timer2

bit 9-8

Unimplemented:

Read as ‘0’

bit 7

ENFLT0:

Fault 0 Input Enable bit

= Fault 0 input is enabled

= Fault 0 input is disabled

bit 6-5

Unimplemented:

Read as ‘0’

bit 4

OCFLT0:

PWM Fault Condition Status bit

= PWM Fault condition has occurred (cleared in HW only)

= No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)

bit 3

TRIGMODE:

Trigger Status Mode Select bit

= TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software

= TRIGSTAT is only cleared by software

bit 2-0

OCM<2:0>:

Output Compare x Mode Select bits(1)

111

= Center-Aligned PWM mode on OCx(2)

110

= Edge-Aligned PWM mode on OCx(2)

101

= Double Compare Continuous Pulse mode: initialize OCx pin low, toggle OCx state continuously

on alternate matches of OCxR and OCxRS

100

= Double Compare Single-Shot mode: initialize OCx pin low, toggle OCx state on matches of OCxR

and OCxRS for one cycle

011

= Single Compare Continuous Pulse mode: compare events continuously toggle OCx pin

010

= Single Compare Single-Shot mode: initialize OCx pin high, compare event forces OCx pin low

001

= Single Compare Single-Shot mode: initialize OCx pin low, compare event forces OCx pin high

000

= Output compare channel is disabled

Note 1:

The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4

“Peripheral Pin Select”

OCFA pin controls OC1-OC4 channels; OCFB pin controls the OC5-OC9 channels. OCxR and OCxRS are

double-buffered only in PWM modes.

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