64GA106 datasheet(129/330 Pages) MICROCHIP

129 / 330 page

 2010 Microchip Technology Inc.

DS39905E-page 129

PIC24FJ256GA110 FAMILY

10.3

Input Change Notification

The input change notification function of the I/O ports

allows the PIC24FJ256GA110 family of devices to gen-

erate interrupt requests to the processor in response to

a change of state on selected input pins. This feature is

capable of detecting input change of states even in

Sleep mode, when the clocks are disabled. Depending

on the device pin count, there are up to 81 external

inputs that may be selected (enabled) for generating an

interrupt request on a change of state.

Registers, CNEN1 through CNEN6, contain the

interrupt enable control bits for each of the CN input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

Each CN pin has both a weak pull-up and a weak

pull-down connected to it. The pull-up acts as a current

source that is connected to the pin, while the pull-down

acts as a current sink that is connected to the pin.

These eliminate the need for external resistors when

push button or keypad devices are connected. The

pull-ups and pull-downs are separately enabled using

the CNPU1 through CNPU6 registers (for pull-ups) and

the CNPD1 through CNPD6 registers (for pull-downs).

Each CN pin has individual control bits for its pull-up

and pull-down. Setting a control bit enables the weak

pull-up or pull-down for the corresponding pin.

When the internal pull-up is selected, the pin pulls up to

VDD – 0.7V (typical). Make certain that there is no

external pull-up source when the internal pull-ups are

enabled, as the voltage difference can cause a current

path.

10.4

Peripheral Pin Select

A major challenge in general purpose devices is provid-

ing the largest possible set of peripheral features while

minimizing the conflict of features on I/O pins. In an

application that needs to use more than one peripheral

multiplexed on a single pin, inconvenient workarounds

in application code or a complete redesign may be the

only option.

The Peripheral Pin Select feature provides an alternative

to these choices by enabling the user’s peripheral set

selection and their placement on a wide range of I/O

pins. By increasing the pinout options available on a par-

ticular device, users can better tailor the microcontroller

to their entire application, rather than trimming the

application to fit the device.

The Peripheral Pin Select feature operates over a fixed

subset of digital I/O pins. Users may independently

map the input and/or output of any one of many digital

peripherals to any one of these I/O pins. Peripheral Pin

Select is performed in software and generally does not

require the device to be reprogrammed. Hardware

safeguards are included that prevent accidental or

spurious changes to the peripheral mapping once it has

been established.

10.4.1

AVAILABLE PINS

The Peripheral Pin Select feature is used with a range

of up to 46 pins, depending on the particular device and

its pin count. Pins that support the Peripheral Pin

Select feature include the designation “RPn” or “RPIn”

in their full pin designation, where “n” is the remappable

pin number. “RP” is used to designate pins that support

both remappable input and output functions, while

“RPI” indicates pins that support remappable input

functions only.

PIC24FJ256GA110 family devices support a larger

number of remappable input only pins than remappable

input/output pins. In this device family, there are up to

32 remappable input/output pins, depending on the pin

count of the particular device selected; these are num-

bered, RP0 through RP31. Remappable input only pins

are numbered above this range, from RPI32 to RPI45

(or the upper limit for that particular device).

See Table 1-4 for a summary of pinout options in each

package offering.

Note:

Pull-ups on change notification pins

should always be disabled whenever the

port pin is configured as a digital output.

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