64GA106 datasheet(128/330 Pages) MICROCHIP

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PIC24FJ256GA110 FAMILY

DS39905E-page 128

 2010 Microchip Technology Inc.

10.1.1

OPEN-DRAIN CONFIGURATION

In addition to the PORT, LAT and TRIS registers for

data control, each port pin can also be individually con-

figured for either digital or open-drain output. This is

controlled by the Open-Drain Control register, ODCx,

associated with each port. Setting any of the bits con-

figures the corresponding pin to act as an open-drain

output.

The open-drain feature allows the generation of

outputs higher than VDD (e.g., 5V) on any desired

digital only pins by using external pull-up resistors. The

maximum open-drain voltage allowed is the same as

the maximum VIH specification.

10.2

Configuring Analog Port Pins

The AD1PCFGL and TRIS registers control the opera-

tion of the A/D port pins. Setting a port pin as an analog

input also requires that the corresponding TRIS bit be

set. If the TRIS bit is cleared (output), the digital output

level (VOH or VOL) will be converted.

When reading the PORT register, all pins configured as

analog input channels will read as cleared (a low level).

Pins configured as digital inputs will not convert an

analog input. Analog levels on any pin that is defined as

a digital input (including the ANx pins) may cause the

input buffer to consume current that exceeds the

device specifications.

10.2.1

I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically, this instruction

would be a NOP.

10.2.2

ANALOG INPUT PINS AND

VOLTAGE CONSIDERATIONS

The voltage tolerance of pins used as device inputs is

dependent on the pin’s input function. Pins that are used

as digital only inputs are able to handle DC voltages up

to 5.5V, a level typical for digital logic circuits. In contrast,

pins that also have analog input functions of any kind

can only tolerate voltages up to VDD. Voltage excursions

beyond VDD on these pins are always to be avoided.

Table 10-1 summarizes the input capabilities. Refer to

Section 28.1 “DC Characteristics”

for more details.

TABLE 10-1:

INPUT VOLTAGE LEVELS(1)

EXAMPLE 10-1:

PORT WRITE/READ EXAMPLE

Note:

For easy identification, the pin diagrams at

the beginning of this data sheet also

indicate 5.5V tolerant pins with dark grey

shading.

Port or Pin

Tolerated

Input

Description

PORTA<10:9>

VDD

Only VDD input

levels tolerated.

PORTB<15:0>

PORTC<15:12>

PORTD<7:6>

PORTF<0>

PORTG<9:6>

PORTA<15:14>,

PORTA<7:0>

5.5V

Tolerates input

levels above

VDD, useful for

most standard

logic.

PORTC<4:1>

PORTD<15:8>,

PORTD<5:0>

PORTE<9:0>

PORTF<13:12>,

PORTF<8:1>

PORTG<15:12>,

PORTG<3:0>

Note 1:

Not all port pins shown here are imple-

mented on 64-pin and 80-pin devices.

Refer to Section 1.0 “Device Overview”

to confirm which ports are available in

specific devices.

MOV

0xFF00, W0

; Configure PORTB<15:8> as inputs

MOV

W0, TRISB

; and PORTB<7:0> as outputs

NOP

; Delay 1 cycle

BTSS

PORTB, #13

; Next Instruction

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