PIC16F882-I datasheet(185/328 Pages) MICROCHIP

185 / 328 page

DS41291F-page 183

PIC16F882/883/884/886/887

13.3

SPI Mode

The SPI mode allows 8 bits of data to be synchronously

transmitted and received, simultaneously. All four modes

of SPI are supported. To accomplish communication,

typically three pins are used:

• Serial Data Out (SDO) – RC5/SDO

• Serial Data In (SDI) – RC4/SDI/SDA

• Serial Clock (SCK) – RC3/SCK/SCL

Additionally, a fourth pin may be used when in any

Slave mode of operation:

• Slave Select (SS) – RA5/SS/AN4

13.3.1

OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control

bits

SSPCON<5:0>

and

SSPSTAT<7:6>.

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock polarity (Idle state of SCK)

• Data input sample phase (middle or end of data

output time)

• Clock edge (output data on rising/falling edge of

SCK)

• Clock rate (Master mode only)

• Slave Select mode (Slave mode only)

Figure 13-1 shows the block diagram of the MSSP

module, when in SPI mode.

FIGURE 13-1:

MSSP BLOCK DIAGRAM

(SPI MODE)

The MSSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR,

until the received data is ready. Once the 8 bits of data

have been received, that byte is moved to the SSPBUF

STAT register and the interrupt flag bit SSPIF of the

PIR1 register are set. This double buffering of the

received data (SSPBUF) allows the next byte to start

reception before reading the data that was just

received. Any write to the SSPBUF register during

transmission/reception of data will be ignored, and the

write collision detect bit WCOL of the SSPCON register

will be set. User software must clear the WCOL bit so

that it can be determined if the following write(s) to the

SSPBUF register completed successfully.

(

)

Read

Write

Internal

Data Bus

SSPSR Reg

SSPM<3:0>

bit 0

Shift

Clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 Output

TOSC

Prescaler

4, 16, 64

Edge

Select

Data to TX/RX in SSPSR

TRIS bit

SMP:CKE

SDI

SDO

SCK

Note: I/O pins have diode protection to VDD and VSS.

SSPBUF Reg

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