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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8347ECVRADDB датащи(PDF) 54 Page - Freescale Semiconductor, Inc |
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MPC8347ECVRADDB датащи(HTML) 54 Page - Freescale Semiconductor, Inc |
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54 / 99 page  MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 54 Freescale Semiconductor Package and Pin Listings Figure 38 and Figure 39 represent the AC timings from Table 54. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 38 shows the SPI timings in slave mode (external clock). Figure 38. SPI AC Timing in Slave Mode (External Clock) Diagram Figure 39 shows the SPI timings in master mode (internal clock). Figure 39. SPI AC Timing in Master Mode (Internal Clock) Diagram 18 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8347EA is available in two packages—a tape ball grid array (TBGA) and a plastic ball grid array (PBGA). See Section 18.1, “Package Parameters for the MPC8347EA TBGA,” Section 18.2, “Mechanical Dimensions for the MPC8347EA TBGA,” Section 18.3, “Package Parameters for the MPC8347EA PBGA,” and Section 18.4, “Mechanical Dimensions for the MPC8347EA PBGA.” 18.1 Package Parameters for the MPC8347EA TBGA The package parameters are provided in the following list. The package type is 35 mm × 35 mm, 672 tape ball grid array (TBGA). Package outline 35 mm × 35 mm Interconnects 672 SPICLK (Input) tNEIXKH tNEIVKH tNEKHOX Input Signals: SPIMOSI (See Note) Output Signals: SPIMISO (See Note) Note: The clock edge is selectable on SPI. SPICLK (Output) tNIIXKH tNIKHOX Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note) Note: The clock edge is selectable on SPI. tNIIVKH |
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