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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8347VRAGDB датащи(PDF) 82 Page - Freescale Semiconductor, Inc |
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MPC8347VRAGDB датащи(HTML) 82 Page - Freescale Semiconductor, Inc |
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82 / 99 page  MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 82 Freescale Semiconductor Clocking VCO divider must be set properly so that the core VCO frequency is in the range of 800–1800 MHz. Table 63. e300 Core PLL Configuration RCWL[COREPLL] core_clk : csb_clk Ratio VCO Divider1 1 Core VCO frequency = core frequency × VCO divider. The VCO divider must be set properly so that the core VCO frequency is in the range of 800–1800 MHz. 0–1 2–5 6 nn 0000 n PLL bypassed (PLL off, csb_clk clocks core directly) PLL bypassed (PLL off, csb_clk clocks core directly) 00 0001 01:1 2 01 0001 01:1 4 10 0001 01:1 8 11 0001 01:1 8 00 0001 1 1.5:1 2 01 0001 1 1.5:1 4 10 0001 1 1.5:1 8 11 0001 1 1.5:1 8 00 0010 02:1 2 01 0010 02:1 4 10 0010 02:1 8 11 0010 02:1 8 00 0010 1 2.5:1 2 01 0010 1 2.5:1 4 10 0010 1 2.5:1 8 11 0010 1 2.5:1 8 00 0011 03:1 2 01 0011 03:1 4 10 0011 03:1 8 11 0011 03:1 8 |
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