ADNS-3050 datasheet(13/31 Pages) PIXART

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Required Timing between Read and Write Commands

There are minimum timing requirements between read and write commands on the serial port.

SCLK

tSWW

WRITE OPERATION

ADDRESS

DATA

WRITE OPERATION

ADDRESS

DATA

Timing between Two Write Commands

If the rising edge of the SCLK for the last data bit of the second write command occurs before the required delay (tSWW),

then the first write command may not complete correctly.

Timing between Write and Read Commands

If the rising edge of SCLK for the last address bit of the read command occurs before the required delay (tSWR), the write

command may not complete correctly.

SCLK

tSWR

WRITE OPERATION

ADDRESS

DATA

NEXT READ OPERATION

ADDRESS

SCLK

tSRAD

READ OPERATION

ADDRESS

NEXT READ

or WRITE OPERATION

ADDRESS

tSRW & tSRR

DATA

Timing between Read and Subsequent Write or Read Commands

During a read operation SCLK should be delayed at least tSRAD after the last address data bit to ensure that the ADNS-

3050 has time to prepare the requested data. The falling edge of SCLK for the first address bit of either the read or write

command must be at least tSRR or tSRW after the last SCLK rising edge of the last data bit of the previous read operation.

Figure 16. Timing between Two Write Commands

Figure 17. Timing between Write and Read Commands

Figure 18. Timing between Read and Subsequent Write or Read Commands

PixArt Imaging Inc.

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

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