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TLC32046MFKB датащи(PDF) 37 Page - Texas Instruments

номер детали TLC32046MFKB
подробное описание детали  Wide-Band Analog Interface Circuit
PDF  56 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

TLC32046MFKB датащи(HTML) 37 Page - Texas Instruments

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3–7
3.5.3
Serial Port – AIC Output Signals, CL = 30 pF for SHIFT CLK Output, CL = 15 pF
For All Other Outputs, TLC32046C and TLC32046I
PARAMETER
MIN
TYP†
MAX
UNIT
tc(SCLK)
Shift clock (SCLK) cycle time
380
ns
tf(SCLK)
Shift clock (SCLK) fall time
3
8
ns
tr(SCLK)
Shift clock (SCLK) rise time
3
8
ns
Shift clock (SCLK) duty cycle
45%
55%
td(CH-FL)
Delay from SCLK
↑ to FSR/FSX/FSD↓
30
ns
td(CH-FH)
Delay from SCLK
↑ to FSR/FSX/FSD↑
35
90
ns
td(CH-DR)
DR valid after SCLK
↑
90
ns
td(CH-EL)
Delay from SCLK
↑ to EODX/EODR↓ in word mode
90
ns
td(CH-EH)
Delay from SCLK
↑ to EODX/EODR↑ in word mode
90
ns
tf(EODX)
EODX fall time
2
8
ns
tf(EODR)
EODR fall time
2
8
ns
td(CH-EL)
Delay from SCLK
↑ to EODX/EODR↓ in byte mode
90
ns
td(CH-EH)
Delay from SCLK
↑ to EODX/EODR↑ in byte mode
90
ns
td(MH-SL)
Delay from MSTR CLK
↑ to SCLK↓
65
170
ns
td(MH-SH)
Delay from MSTR CLK
↑ to SCLK↑
65
170
ns
† Typical values are at TA = 25°C.
3.5.4
Serial Port – AIC Output Signals, CL = 30 pF for SHIFT CLK Output, CL = 15 pF
For All Other Outputs, TLC32046M
PARAMETER
MIN
TYP†
MAX
UNIT
tc(SCLK)
Shift clock (SCLK) cycle time
400
ns
tf(SCLK)
Shift clock (SCLK) fall time
3
ns
tr(SCLK)
Shift clock (SCLK) rise time
3
ns
Shift clock (SCLK) duty cycle
45%
55%
td(CH-FL)
Delay from SCLK
↑ to FSR/FSX/FSD↓
30
250
ns
td(CH-FH)
Delay from SCLK
↑ to FSR/FSX/FSD↑
35
250
ns
td(CH-DR)
DR valid after SCLK
↑
250
ns
td(CH-EL)
Delay from SCLK
↑ to EODX/EODR↓ in word mode
250
ns
td(CH-EH)
Delay from SCLK
↑ to EODX/EODR↑ in word mode
250
ns
tf(EODX)
EODX fall time
2
ns
tf(EODR)
EODR fall time
2
ns
td(CH-EL)
Delay from SCLK
↑ to EODX/EODR↓ in byte mode
250
ns
td(CH-EH)
Delay from SCLK
↑ to EODX/EODR↑ in byte mode
250
ns
td(MH-SL)
Delay from MSTR CLK
↑ to SCLK↓
65
170
ns
td(MH-SH)
Delay from MSTR CLK
↑ to SCLK↑
65
170
ns
† Typical values are at TA = 25°C.



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