STP16CPC26

Timing diagrams

Doc ID 18469 Rev 4

13/26

Figure 12.

Timing for clock signal, serial-in and serial out data

The correct sampling of the data depends on the stability of the data at SDI on the rising

edge of the clock signal and it is assured by a proper data setup and hold time (t

SETUP1

And

t

HOLD

), as shown in

Figure 12. The same figure shows the propagation delay from CLK to

SDO (t

PLH

/t

PHL

).

Figure 13 describes the setup times for LE and OE signals (t

SETUP2

and t

SETUP3

respectively), the minimum duration of these signals (t

WLAT

and t

WENA

respectively) and the

propagation delay from CLK to OUT

n

, LE to OUT

n

and OE to OUT

n

(t

PLH1

/t

PHL1

, t

PLH2

/t

PHL2

and t

PLH3

/t

PHL3

respectively).

Finally

Figure 14 defines the turn-on and turn-off time (t

r

and t

f

) of the current generators.

Table 7.

Truth table

CLOCK

LE

OE

1.

OUTn = ON when Dn = H, OUTn = OFF when Dn = L

SDO

H

L

Dn

Dn ..... Dn - 7 ..... Dn -15

Dn - 15

L

L

Dn + 1

No change

Dn - 14

H

L

Dn + 2

Dn + 2 ..... Dn - 5 ..... Dn -13

Dn - 13

X

L

Dn + 3

Dn + 2 ..... Dn - 5 ..... Dn -13

Dn - 13

X

H

Dn + 3

OFF

Dn - 13