L7C109 datasheet(14/15 Pages) LODEV

14 / 15 page

LOGIC Devices Incorporated

www.logicdevices.com

Feb 17, 2012 LDS-L7C108/9-G

1M Static RAMs

128K x 8 Static RAM

L7C108

L7C109

NOTES

1. Maximum Ratings indicate stress specifica-

tions only. Functional operation of these products

at values beyond those indicated in the Operat-

ing Conditions table is not implied. Exposure to

maximum rating conditions for extended periods

may affect reliability of the tested device.

2. The products described by this specifica-

tion include internal circuitry designed to pro-

tect the chip from damaging substrate injection

currents and accumulations of static charge.

Nevertheless, conventional precautions should

be observed during storage, handling, and use

of these circuits in order to avoid exposure to

excessive electrical stress values.

3. This product provides hard clamping of tran-

sient undershoot. Input levels below ground will

be clamped beginning at –0.6 V. A current in

excess of 100 mA is required to reach –2.0 V.

The device can withstand indefinite operation

with inputs as low as –3 V subject only to power

dissipation and bond wire fusing constraints.

4. Tested with GND VOUT VCC. The device is

disabled, i.e., CE1 = VCC, CE2 = GND.

5. A series of normalized curves is available to

supply the designer with typical DC and AC

parametric information for Logic Devices Static

RAMs. These curves may be used to determine

device characteristics at various temperatures

and voltage levels.

6. Tested with all address and data inputs chang-

ing at the maximum cycle rate. The device is con-

tinuously enabled for reading, i.e., CE1 VIL, CE2

VIH, WE VIH, with outputs disabled, OE VIH.

Input pulse levels are 0 to 3.0 V.

7. Tested with outputs open and all address and

data inputs stable. The device is continuously

disabled, i.e., CE1 VIH, CE2 VIL.

8. Tested with outputs open and all address and

data inputs stable. The device is continuously

disabled, i.e. CE1 = VCC, CE2 = GND. Input

levels are within 0.2 V of VCC or GND.

9. Data retention operation requires that VCC

never drop below 2.0V. CE1 must be

VCC -

0.2 V or CE2 must be

0.2 V. All other inputs

must meet VIN

VCC - 0.2 V or VIN

0.2 V to

CE2, and WE; there are no restrictions on data

and address.

10. These parameters are guaranteed but not

100% tested.

11. Test conditions assume input transition times

of less than 3 ns, reference levels of 1.5 V, output

loading for specified IOL and IO

12. Each parameter is shown as a minimum or

maximum value. Input requirements are speci-

fied from the point of view of the external system

driving the chip. For example, tAVEW is specified

as a minimum since the external system must

supply at least that much time to meet the worst-

case requirements of all parts. Responses from

the internal circuitry are specified from the point

of view of the device. Access time, for example,

is specified as a maximum since worst-case

operation of any device always provides data

within that time.

13. WE is high for the read cycle.

low,

CE2

15. All address lines are valid prior-to or coinci-

dent-with the CE1 and CE2 transition to active.

16. The internal write cycle of the memory is

defined by the overlap of CE1 and CE2 active

and WE low. All three signals must be active to

initiate a write. Any signal can terminate a write

by going inactive. The address, data, and control

input setup and hold times should be referenced

to the signal that becomes active last or becomes

inactive first.

17. If WE goes low before or concurrent with the

latter of CE1 and CE2 going active, the output

remains in a high impedance state.

18. If CE1 and CE2 goes inactive before or con-

current with WE going high, the output remains in

a high impedance state.

19. Powerup from ICC2 to ICC1 occurs as a result

of any of the following conditions:

a. Rising edge of CE2

edge of CE1

, CE2

, CE

, CE2, and

The device automatically powers down from ICC1

to ICC2 after tPD has elapsed from any of the prior

conditions. This means that power dissipation is

dependent on only cycle rate, and is not on Chip

Select pulse width.

20. At any given temperature and voltage con-

dition, output disable time is less than output

enable time for any given device.

21. Transition is measured ±200 mV from steady

state voltage with specified loading in Fig. 1b.

This parameter is sampled and not 100% tested.

22. All address timings are referenced from the

last valid address line to the first transitioning

address line.

23. CE1, CE2, or WE must be inactive during

address transitions.

24. This product is a very high speed device and

care must be taken during testing in order to real-

ize valid test information. Inadequate attention to

setups and procedures can cause a good part

to be rejected as faulty. Long high inductance

leads that cause supply bounce must be avoided

by bringing the VCC and ground planes directly

up to the contactor fingers. A 0.01 μF high fre-

quency capacitor is also required between VCC

and ground. To avoid signal reflections, proper

terminations must be used.

+5 V

OUTPUT

R1 480

30 pF

255

INCLUDING

JIG AND

SCOPE

<3 ns

GND

+3.0 V

90%

10%

90%

10%

<3 ns

+5 V

OUTPUT

5 pF

INCLUDING

JIG AND

SCOPE

R1 480

255

Figure 1a.

Figure 1b.

Figure 2

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