AM188ES-40VCSLASHW datasheet(49/102 Pages) AMD

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Am186/188ES and Am186/188ESLV Microcontrollers

P R E L IMINA R Y

Watchdog Timer

The Am186ES and Am188ES microcontrollers provide

a true watchdog timer function. The Watchdog Timer

(WDT) can be used to regain control of the system

when software fails to respond as expected. The WDT

is active after reset. It can only be modified a single

time by a keyed sequence of writes to the watchdog

timer control register (WDTCON) following reset. This

single write can either disable the timer or modify the

timeout period and the action taken upon timeout. A

keyed sequence is also required to reset the current

WDT count. This behavior ensures that randomly exe-

cuting code will not prevent a WDT event from occur-

ring.

The WDT supports up to a 1.67-second timeout period

in a 40-MHz system. After reset, the WDT is enabled

and the timeout period is set to its maximum value.

The WDT can be configured to cause either an NMI in-

terrupt or a system reset upon timeout. If the WDT is

configured for NMI, the NMIFLAG in the WDTCON reg-

ister is set when the NMI is generated. The NMI inter-

rupt service routine (ISR) should examine this flag to

determine if the interrupt was generated by the WDT or

by an external source. If the NMIFLAG is set, the ISR

should clear the flag by writing the correct keyed se-

quence to the WDTCON register. If the NMIFLAG is set

when a second WDT timeout occurs, a WDT system

reset is generated rather than a second NMI event.

When the processor takes a WDT reset, either due to

a single WDT event with the WDT configured to gener-

ate resets or due to a WDT event with the NMIFLAG

set, the RSTFLAG in the WDTCON register is set. This

allows system initialization code to differentiate be-

tween a hardware reset and a WDT reset and take ap-

propriate action. The RSTFLAG is cleared when the

WDTCON register is read or written. The processor

does not resample external pins during a WDT reset.

This means that the clocking, the reset configuration

able during reset do not change when a WDT system

reset occurs. All other activities are identical to those of

a normal system reset.

Note: The Watchdog Timer (WDT) is active after re-

set.

DIRECT MEMORY ACCESS (DMA)

Direct memory access (DMA) permits transfer of data

between memory and peripherals without CPU involve-

ment. The DMA unit in the Am186ES and Am188ES

microcontrollers, shown in Figure 10, provides two

high-speed DMA channels. Data transfers can occur

between memory and I/O spaces (e.g., memory to I/O)

or within the same space (e.g., memory to memory or

I/O to I/O). The DMA channels can be directly con-

nected to the asynchronous serial ports.

Either bytes or words can be transferred to or from

even or odd addresses on the Am186ES microcon-

troller. However, the Am186ES microcontroller does

not support word DMA transfers to or from memory

configured for 8-bit accesses. The Am188ES micro-

controller does not support word transfers. Only two

bus cycles (a minimum of eight clocks) are necessary

for each data transfer.

Each channel accepts a DMA request from one of four

sources: the channel request pin (DRQ1–DRQ0),

Timer 2, a serial port, or the system software. The

channels can be programmed with different priorities in

the event of a simultaneous DMA request or if there is

a need to interrupt transfers on the other channel.

DMA Operation

Each channel has six registers in the peripheral control

block that define specific channel operations. The DMA

registers consist of a 20-bit source address (two regis-

ters), a 20-bit destination address (two registers), a 16-

bit transfer count register, and a 16-bit control register.

The DMA transfer count register (DTC) specifies the

number of DMA transfers to be performed. Up to 64K

of byte or word transfers can be performed with auto-

matic termination. The DMA control registers define the

channel operation. All registers can be modified dur-

ing any DMA activity. Any changes made to the DMA

registers are reflected immediately in DMA operation.

Table 8.

Am186ES Microcontroller Maximum

DMA Transfer Rates

Type of Synchronization

Selected

Maximum DMA

Transfer Rate (Mbytes)

MHz

Unsynchronized

8.25

6.25

Source Synch

8.25

6.25

Destination Synch

(CPU needs bus)

6.6

5.5

4.16

3.3

Destination Synch

(CPU does not need bus)

6.6

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