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AM79C975KCW датащи(PDF) 91 Page - Advanced Micro Devices |
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AM79C975KCW датащи(HTML) 91 Page - Advanced Micro Devices |
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91 / 304 page ![]() Am79C973/Am79C975 91 P R E L I M INARY pansion ROM data are stored in holding registers. One clock cycle after the last data byte is available, the Am79C973/Am79C975 controller asserts TRDY. The access time for the Expansion ROM or the EB- DATA (BCR30) device (tACC) during read operations can be calculated by subtracting the clock to output delay for the EBUA_EBA[7:0] outputs (tv_A_D) and by subtracting the input to clock setup time for the EBD[7:0] inputs (ts_D) from the time defined by ROMTMG: tACC = ROMTMG * CLK period *CLK_FAC - (tv_A_D) - (ts_D) Figure 40. Flash Configuration for the Expansion Bus The access time for the Expansion ROM or for the EB- DATA (BCR30) device (tACC) during write operations can be calculated by subtracting the clock to output delay for the EBUA EBA[7:0] outputs (tv_A_D) and by adding the input to clock setup time for Flash/EPRO in- puts (ts_D) from the time defined by ROMTMG: tACC = ROMTMG * CLK period * CLK_FAC - (tv_A_D) - (ts_D) The timing diagram in Figure 43 assumes the default programming of ROMTMG (1001b = 9 CLK). After reading the first byte, the Am79C973/Am79C975 con- troller reads in three more bytes by incrementing the lower portion of the ROM address. After the last byte is strobed in, TRDY will be asserted on clock 50. When the host tries to perform a burst read of the Expansion ROM, the Am79C973/Am79C975 controller will dis- connect the access at the second data phase. The host must program the Expansion ROM Base Ad- dress register in the PCI configuration space before the first access to the Expansion ROM. The Am79C973/ EBUA_EBA[7:0] EBDA[15:8] EBD[7:0] EBWE AS_/EBOE A[15:8] A[7:0] DQ[7:0] OE CS Am79C973 '374 D-FF FLASH EROMCS A[23:16] WE 21510D-45 |
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