AM79C971VCW datasheet(168/265 Pages) AMD

168 / 265 page

168

Am79C971

P R E L I M INARY

sertion of DEVSEL and STOP

while TRDY is not asserted, sig-

naling to the initiator to discon-

nect and retry the access at a

later time.

If a PREAD command is given to

the Am79C971 controller but no

EEPROM is attached to the inter-

face pins, the PREAD bit will be

cleared to a 0, and the PVALID bit

will remain reset with a value of 0.

This applies to the automatic

read

the

EEPROM

after

H_RESET as well as to host initi-

ated PREAD commands. EE-

PROM programmable locations

on board the Am79C971 control-

ler will be set to their default val-

ues by such an aborted PREAD

operation. For example, if the

aborted PREAD operation imme-

diately followed the H_RESET

operation, then the final state of

the EEPROM programmable lo-

cations will be equal to the

H_RESET

programming

for

those locations.

If a PREAD command is given to

the Am79C971 controller and the

auto-detection pin (EESK/LED1/

SFBD) indicates that no EE-

PROM is present, then the EE-

PROM read operation will still be

attempted.

Note that at the end of the

H_RESET operation, a read of

the EEPROM will be performed

automatically. This H_RESET-

generated EEPROM read func-

tion will not proceed if the auto-

detection pin (EESK/LED1/SF-

BD) indicates that no EEPROM is

present.

Read accessible always; write

accessible only when either the

STOP or the SPND bit is set.

PREAD

set

during

H_RESET and is unaffected by

S_RESET or the STOP bit.

EEDET

EEPROM Detect. This bit indi-

cates the sampled value of the

EESK/LED1/SFBD pin at the end

of H_RESET. This value indi-

cates whether or not an EE-

PROM is present at the EEPROM

interface. If this bit is a 1, it indi-

cates

that

EEPROM

present. If this bit is a 0, it indi-

cates that an EEPROM is not

present.

Read accessible only. EEDET is

read only; write operations have

no effect. The value of this bit is

determined at the end of the

H_RESET operation. It is unaf-

fected by S_RESET or the STOP

bit.

Table 34 indicates the possible

combinations of EEDET and the

existence of an EEPROM and the

resulting operations that are pos-

sible on the EEPROM interface.

12-5

RES

Reserved locations. Written as

zeros; read as undefined.

EEN

EEPROM Port Enable. When this

bit is set to a 1, it causes the val-

ues of ECS, ESK, and EDI to be

driven onto the EECS, EESK,

and EEDI pins, respectively. If

EEN = 0 and no EEPROM read

function is currently active, then

EECS will be driven LOW. When

EEN = 0 and no EEPROM read

function is currently active, EESK

and EEDI pins will be driven by

the LED registers BCR5 and

BCR4, respectively. See Table

35.

Read accessible always, write

accessible only when either the

STOP or the SPND bit is set.

EEN is set to 0 by H_RESET and

is unaffected by the S_RESET or

STOP bit.

RES

Reserved location. Written as

zero and read as undefined.

ECS

EEPROM Chip Select. This bit is

used to control the value of the

EECS pin of the interface when

the EEN bit is set to 1 and the

PREAD bit is set to 0. If EEN = 1

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