AM79C971VCW datasheet(146/265 Pages) AMD

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Am79C971

P R E L I M INARY

a different ID as that stored in the

Device ID register in the PCI con-

figuration space.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. PARTID is read

only. Write operations are ig-

nored.

11-1

MANFID

Manufacturer ID. The 11-bit man-

ufacturer

code

for

AMD

00000000001b. This code is per

the JEDEC Publication 106-A.

Note that this code is not the

same as the Vendor ID in the PCI

configuration space.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. MANFID is

read only. Write operations are

ignored.

ONE

Always a logic 1.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. ONE is read

only. Write operations are ig-

nored.

CSR89: Chip ID Register Upper

Bit

Name

Description

31-16 RES

Reserved locations. Read as un-

defined.

15-12 VER

Version. This 4-bit pattern is

silicon-revision dependent.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. VER is read

only. Write operations are ig-

nored.

11-0

PARTIDU

Upper 12 bits of the Am79C971

controller part number, i.e., 0010

0110 0010b (262h).

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. PARTIDU is

read only. Write

operations are

ignored.

CSR92: Ring Length Conversion

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

RCON

Ring Length Conversion Regis-

ter. This register performs a ring

length conversion from an encod-

ed value as found in the initializa-

tion block to a two’s complement

value used for internal counting.

By writing bits 15-12 with an en-

coded ring length, a two’s com-

plemented value is read. The

RCON register is undefined until

written.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

CSR100: Bus Timeout

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

MERRTO

This register contains the value of

the longest allowable bus latency

(interval between assertion of

REQ and assertion of GNT) that a

system

may

insert

into

Am79C971

controller

master

transfer. If this value of bus laten-

cy is exceeded, then a MERR will

be indicated in CSR0, bit 11, and

an interrupt may be generated,

depending upon the setting of the

MERRM bit (CSR3, bit 11) and

the IENA bit (CSR0, bit 6).

The value in this register is inter-

preted as the unsigned number of

XTAL1 clock periods divided by

two, (i.e., the value in this register

is given in 0.1

µs increments.) For

example, the value 0600h (1536

decimal) will cause a MERR to be

indicated after 153.6

µs of bus la-

tency. A value of 0 will allow an

infinitely long bus latency, i.e.,

bus timeout error will never oc-

cur.

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