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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C971VCW датащи(PDF) 130 Page - Advanced Micro Devices |
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AM79C971VCW датащи(HTML) 130 Page - Advanced Micro Devices |
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130 / 265 page  130 Am79C971 15-0 PADR[15:0] Physical Address Register, PADR[15:0]. The content of this register is undefined until loaded from the initialization block after the INIT bit in CSR0 has been set or a direct register write has been performed on this register. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR13: Physical Address Register 1 Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 PADR[31:16] Physical Address Register, PADR[31:16]. The content of this register is undefined until loaded from the initialization block after the INIT bit in CSR0 has been set or a direct register write has been performed on this register. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR14: Physical Address Register 2 Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 PADR[47:32] Physical Address Register, PADR[47:32]. The content of this register is undefined until loaded from the initialization block after the INIT bit in CSR0 has been set or a direct register write has been performed on this register. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR15: Mode This register’s fields are loaded during the Am79C971 controller initialization routine with the corresponding Initialization Block values, or when a direct register write has been performed on this register. Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15 PROM Promiscuous Mode. When PROM = 1, all incoming receive frames are accepted. Read/Write accessible only when either the STOP or the SPND bit is set. 14 DRCVBC Disable Receive Broadcast. When set, disables the Am79C971 controller from re- ceiving broadcast messages. Used for protocols that do not support broadcast addressing, except as a function of multicast. DRCVBC is cleared by activation of H_RESET or S_RESET (broadcast messages will be re- ceived) and is unaffected by STOP. Read/Write accessible only when either the STOP or the SPND bit is set. 13 DRCVPA Disable Receive Physical Ad- dress. When set, the physical ad- dress detection (Station or node ID) of the Am79C971 controller will be disabled. Frames ad- dressed to the nodes individual physical address will not be rec- ognized. Read/Write accessible only when either the STOP or the SPND bit is set. 12 DLNKTST Disable Link Status. When DLNKTST = 1, monitoring of Link Pulses is disabled. When DLNKTST = 0, monitoring of Link Pulses is enabled. This bit only has meaning when the 10BASE- T network interface is selected. Read/Write accessible only when either the STOP or the SPND bit is set. 11 DAPC Disable Automatic Polarity Cor- rection. When DAPC = 1, the |
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