AM79C971VCW datasheet(117/265 Pages) AMD

117 / 265 page

Am79C971

117

Read accessible always. INTR is

read only. INTR is cleared by

clearing all of the active individual

interrupt bits that have not been

masked out.

IENA

Interrupt Enable allows INTA to

be active if the Interrupt Flag is

set. If IENA = 0, then INTA will be

disabled regardless of the state

of INTR.

Read/Write accessible always.

IENA is set by writing a 1 and

cleared by writing a 0. IENA is

cleared

H_RESET

S_RESET and setting the STOP

bit.

RXON

Receive On indicates that the re-

ceive function is enabled. RXON

is set if DRX (CSR15, bit 0) is set

to 0 after the START bit is set. If

INIT and START are set together,

RXON will not be set until after

the initialization block has been

read in.

Read accessible always. RXON

is read only. RXON is cleared by

H_RESET or S_RESET and set-

ting the STOP bit.

TXON

Transmit On indicates that the

transmit

function

enabled.

TXON is set if DTX (CSR15, bit 1)

is set to 0 after the START bit is

set. If INIT and START are set to-

gether, TXON will not be set until

after the initialization block has

been read in.

Read accessible always. TXON

is read only. TXON is cleared by

H_RESET or S_RESET and set-

ting the STOP bit.

TDMD

Transmit Demand, when set,

causes the Buffer Management

Unit to access the Transmit De-

scriptor Ring without waiting for

the poll-time counter to elapse. If

TXON is not enabled, TDMD bit

will be reset and no Transmit De-

scriptor Ring access will occur.

TDMD is required to be set if the

TXDPOLL bit in CSR4 is set. Set-

ting TDMD while TXDPOLL = 0

merely hastens the Am79C971

controller’s response to a Trans-

mit Descriptor Ring Entry.

Read/Write accessible always.

TDMD is set by writing a 1. Writ-

ing a 0 has no effect. TDMD will

be cleared by the Buffer Manage-

ment Unit when it fetches a

Transmit Descriptor. TDMD is

cleared

H_RESET

S_RESET and setting the STOP

bit.

STOP

STOP assertion disables the chip

from all DMA activity. The chip re-

mains inactive until either STRT

or INIT are set. If STOP, STRT

and INIT are all set together,

STOP will override STRT and

INIT.

Read/Write accessible always.

STOP is set by writing a 1, by

H_RESET or S_RESET. Writing

a 0 has no effect. STOP is

cleared by setting either STRT or

INIT.

STRT

assertion

enables

Am79C971 controller to send and

receive frames, and perform buff-

er management operations. Set-

ting STRT clears the STOP bit. If

STRT and INIT are set together,

the Am79C971 controller initial-

ization will be performed first.

Read/Write accessible always.

STRT is set by writing a 1. Writing

a 0 has no effect. STRT is cleared

by H_RESET, S_RESET, or by

setting the STOP bit.

INIT

assertion

enables

the

Am79C971 controller to begin the

initialization

procedure

which

reads in the initialization block

from memory. Setting INIT clears

the STOP bit. If STRT and INIT

are set together, the Am79C971

controller initialization will be per-

formed first. INIT is not cleared

when the initialization sequence

has completed.

Read/Write accessible always.

INIT is set by writing a 1. Writing

a 0 has no effect. INIT is cleared

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