AM79C971VCW datasheet(110/265 Pages) AMD

110 / 265 page

110

Am79C971

• In master mode, during the data

phase of all memory read com-

mands.

In master mode, during the data

phase of the memory write com-

mand, the Am79C971 controller

sets the PERR bit if the target re-

ports a data parity error by as-

serting the PERR signal.

PERR is not effected by the state

of the Parity Error Response en-

able bit (PCI Command register,

bit 6).

PERR is set by the Am79C971

controller and cleared by writing a

1. Writing a 0 has no effect.

PERR is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

SERR

Signaled SERR. SERR is set

when the Am79C971 controller

detects an address parity error

and both SERREN and PERREN

(PCI Command register, bits 8

and 6) are set.

SERR is set by the Am79C971

controller and cleared by writing a

1. Writing a 0 has no effect.

SERR is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

RMABORT Received

Master

Abort.

RM-

ABORT

set

when

the

Am79C971 controller terminates

a master cycle with a master

abort sequence.

RMABORT

set

the

Am79C971

controller

and

cleared by writing a 1. Writing a 0

has no effect. RMABORT is

cleared by H_RESET and is not

affected by S_RESET or by set-

ting the STOP bit.

RTABORT

Received

Target

Abort.

RT-

ABORT is set when a target ter-

minates an Am79C971 master

cycle with a target abort se-

quence.

RTABORT

set

the

Am79C971

controller

and

cleared by writing a 1. Writing a 0

has

effect.

RTABORT

cleared by H_RESET and is not

affected by S_RESET or by set-

ting the STOP bit.

STABORT

Send Target Abort. Read as ze-

ro; write operations have no ef-

fect. The Am79C971 controller

will never terminate a slave ac-

cess with a target abort se-

quence.

STABORT is read only.

10-9

DEVSEL

Device Select Timing. DEVSEL

is set to 01b (medium), which

means that the Am79C971 con-

troller will assert DEVSEL two

clock periods after FRAME is as-

serted.

DEVSEL is read only.

DATAPERR

Data

Parity

Error

Detected.

DATAPERR is set when the

Am79C971 controller is the cur-

rent bus master and it detects a

data parity error and the Parity

Error Response enable bit (PCI

Command register, bit 6) is set.

During the data phase of all

memory read commands, the

Am79C971 controller checks for

parity error by sampling the

AD[31:0] and C/BE[3:0] and the

PAR lines. During the data phase

of all memory write commands,

the Am79C971 controller checks

the PERR input to detect whether

the target has reported a parity

error.

DATAPERR

set

the

Am79C971

controller

and

cleared by writing a 1. Writing a 0

has no effect. DATAPERR is

cleared by H_RESET and is not

affected by S_RESET or by set-

ting the STOP bit.

FBTBC

Fast

Back-To-Back

Capable.

Read as one; write operations

have no effect. The Am79C971

controller is capable of accepting

fast

back-to-back

transactions

with the first transaction address-

ing a different target.

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