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AM79C971VCW датащи(PDF) 260 Page - Advanced Micro Devices

номер детали AM79C971VCW
подробное описание детали  PCnet??FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
PDF  265 Pages
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производитель  AMD [Advanced Micro Devices]
домашняя страница  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C971VCW датащи(HTML) 260 Page - Advanced Micro Devices

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I-2
BCR6
LED2 Status
157
BCR7
LED3 Status
160
BCR9
Full-Duplex Control
163
Bus Master DMA Transfers
37
C
Carrier Tracking and End of Message
71
Clock Acquisition
71
Collision Detection
72
Collision Handling
63
Compatible (with Am79C971 device)
10BASE-T Filters and Transformers
A-1
AUI Isolation Transformers
A-2
DC/DC Converters
A-2
Media Interface Modules
A-1
Control and Status Registers
115–148
CSR0
Am79C971 Controller Status and
Control Register
115
CSR1
Initialization Block Address 0
118
CSR10
Logical Address Filter 2
129
CSR100
Bus Timeout
146
CSR11
Logical Address Filter 3
129
CSR112
Missed Frame Count
147
CSR114
Receive Collision Count
147
CSR12
Physical Address Register 0
129
CSR122
Advanced Feature Control
147
CSR124
Test Register 1
147
CSR125
MAC Enhanced Configuration Control
147
CSR13
Physical Address Register 1
130
CSR14
Physical Address Register 2
130
CSR15
Mode
130
CSR16
Initialization Block Address Lower
133
CSR17
Initialization Block Address Upper
133
CSR18
Current Receive Buffer Address Lower 133
CSR19
Current Receive Buffer Address Upper 133
CSR2
Initialization Block Address 1
118
CSR20
Current Transmit Buffer Address Lower 133
CSR21
Current Transmit Buffer Address Upper 133
CSR22
Next Receive Buffer Address Lower
134
CSR23
Next Receive Buffer Address Upper
134
CSR24
Base Address of Receive Ring Lower
134
CSR25
Base Address of Receive Ring Upper
134
CSR26
Next Receive Descriptor Address Lower134
CSR27
Next Receive Descriptor Address Upper134
CSR28
Current Receive Descriptor Address
Lower
134
CSR29
Current Receive Descriptor Address
Upper
135
CSR3
Interrupt Masks and Deferral Control
118
CSR30
Base Address of Transmit Ring Lower
135
CSR31
Base Address of Transmit Ring Upper
135
CSR32
Next Transmit Descriptor Address Lower135
CSR33
Next Transmit Descriptor Address Upper135
CSR34
Current Transmit Descriptor Address Lower
135
CSR35
Current Transmit Descriptor Address
135
CSR36
Next Next Receive Descriptor Address
136
CSR37
Next Next Receive Descriptor Address
Upper
136
CSR38
Next Next Transmit Descriptor Address Lower
136
CSR39
Next Next Transmit Descriptor Address Upper
136
CSR4
Test and Features Control
121
CSR40
Current Receive Byte Count
136
CSR41
Current Receive Status
136
CSR42



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