AM79C971VCW datasheet(254/265 Pages) AMD

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F-2

Symptom: Part A - On the first attempt of reading CSR30, the system will suffer a PCI Retry. A subsequent

CSR30 access will be allowed to read the correct CSR30 data. Part B - If the LAAINC (BCR29, bit 14) bit is

set, and if a CSR30 read access is in the middle of a series of continuous reads of BCR30 for SRAM/Flash

access, the CSR30 access causes the SRAM/Flash address to auto-increment.

Implication: Part A - This is a minor erratum with no impact on the system. The PCI Retry does not cause

any system errors and will automatically recover. Part B - The system-level exposure to this problem is very

minimal. There is no exposure or customers of AMD’s PCnet drivers, because AMD’s drivers do not perform

CSR30 reads. For those developing proprietary diagnostic software routines, please follow the workaround

recommended below.

Workaround: Part A - None needed and none available. Part B - Disable the LAAINC bit prior to executing

the specific register access sequence outlined in the symptom statement; LAAINC bit may be enabled subse-

quent to executing the CSR30 read access.

Status: No current plan to fix this erratum.

Symptom: In a high traffic network and with SRAM on and in 10Mbps mode, the babble error bit occasionally

gets set erroneously; no transmitter babbles are observed on the wire.

Implication: Some diagnostics software will report false babbles. No impact for customers who utilize the

PCnet family drivers since PCnet drivers do not report babble errors.

Workaround: Ignore the babble errors.

Status: No current plan to fix this erratum.

Symptom: In an excessively high collision network, the device occasionally set the LCOL bit erroneously in

10Mbps mode with external SRAM enabled.

Implication: No discernible performance impact. Problem has only been observed in lab set up. Some diag-

nostics software will report false LCOL errors.

Workaround: None.

Status: No current plan to fix this erratum.

Symptom: When PCnet-FAST receives a frame on the MII port with correct FCS followed by exactly one nib-

ble with RX_ER asserted, it does not report a FCS error.

Implication: None in an 802.3 compliant network. Observable in custom diagnostic tests for End of Shell De-

limiter (ESD) only.

Workaround: None.

Status: No current plan to fix this erratum.

Symptom: When RCVE bit (bit 2, CSR4, 5, 6, and 7) is set and the MII port is selected, the LED output does

not indicate the correct receive status. This bit functions correctly for the internal 10 BASE-T and AUI ports.

Implication: LED output will not be asserted based on the receive activities at the MII port.

Workaround: Use RCVME bit (bit 5, CSR 4, 5, 6 and 7) in place of the RCVE bit for proper LED receive status

indication. The RCVME bit enables the indication of all received packets which pass the address match func-

tion for this node, whereas the RCVE bit enables the indication of all packets received.

Status: No current plan to fix this erratum.

Symptom: During reception of a packet, if the CRS input to the device is de-asserted two RX_CLK times be-

fore the end of RX_DV, message byte counter (MCNT) will indicates one less byte and the last byte of the CRC

will be corrupt. If the CRS is de-asserted three or more RX_CLK times before the end of RX_DV, the CRC

error bit will be set and the packet will be lost.

Implication: Network performance might vary from normal to sluggish to no connection depending on the se-

verity and the rate of occurrence.

Workaround: The workaround for this problem is to OR the RX_DV and CSR signals from external PHY and

feed the output to the CRS input of the PCnet-FAST.

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