| поискавой системы для электроныых деталей |
|
AM79C971VCW датащи(PDF) 203 Page - Advanced Micro Devices |
|
|
|||||||||||||||||||||||||||||
AM79C971VCW датащи(HTML) 203 Page - Advanced Micro Devices |
|
203 / 265 page ![]() Am79C971 203 3. VOH does not apply to open-drain output pins. 4. OH1 applies to all other outputs. IOH2 applies to TXD[3:0], TX_EN,TX_ER,MDC, and MDIO Outputs are CMOS and will be driven to rail if the load is not resistive. 5. IL and IIH apply to all input pins except XTAL1. 6. OZL and IOZH apply to all three-state output pins and bidirectional pins. 7. Parameter not tested. Value determined by characterization. 8. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands. 9. Correlated to other tested parameters - not tested directly. 10. Test not implemented to data sheet specification. 11. CIN = 8 pF for the IDSEL input and all input pins on the MII interface (TX_CLK, COL, CRS, RX_CLK, RXD[3:0], RX_DV, RX_ER). 12. The power supply current in Magic Packet mode is linear with respect to the PCI Clock frequency operation, assuming the network port remains constant. For example, at CLK = 20 MHz, the maximum Magic Packet power supply current would be 87 mA. SWITCHING CHARACTERISTICS: BUS INTERFACE Parameter Symbol Parameter Name Test Condition Min Max Unit Clock Timing - PCI Bus Interface FCLK CLK Frequency 0 33 MHz tCYC CLK Period @ 1.5 V for VDDB = 5 V @ 0.4 VDD_PCI V for VDD_PCI = 3.3 V 30 _ ns tHIGH CLK High Time @ 2.0 V for VDDB = 5 V @ 0.475 VDD_PCI V for VDD_PCI = 3.3 V 12 ns tLOW CLK Low Time @ 0.8 V for VDDB = 5 V @ 0.325 VDD_PCI V for VDD_PCI = 3.3 V 12 ns tFALL CLK Fall Time over 2 V p-p for VDDB = 5 V over 0.4 VDD_PCI p-p for VDD_PCI = 3.3 V (Note 1) 1 4 V/ns tRISE CLK Rise Time over 2 V p-p for VDDB = 5 V over 0.4 VDD_PCI p-p for VDD_PCI = 3.3 V (Note 1) 1 4 V/ns Output and Float Delay Timing - PCI Bus Interface tVAL AD[31:00], C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, DEVSEL, PERR, SERR Valid Delay 2 11 ns tVAL (REQ) REQ Valid Delay 2 12 ns tON AD[31:00], C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, DEVSEL Active Delay 2 ns tOFF AD[31:00], C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, DEVSEL Float Delay 28 ns |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |