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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C970AVCW датащи(PDF) 40 Page - Advanced Micro Devices |
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AM79C970AVCW датащи(HTML) 40 Page - Advanced Micro Devices |
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40 / 219 page  AMD P R E L I M I N A R Y 40 Am79C970A Parity Error Response When the PCnet-PCI II controller is not the current bus master, it samples the AD[31:0], C/ BE[3:0] and the PAR lines during the address phase of any PCI command for a parity error. When it detects an address parity error, the controller sets PERR (PCI Status register, bit 15) to ONE. When reporting of that error is enabled by setting SERREN (PCI Command register, bit 8) and PERREN (PCI Command register, bit 6) to ONE, the Pcnet-PCI II controller also drives the SERR signal low for one clock cycle and sets SERR (PCI Status register, bit 14) to ONE. The assertion of SERR follows the address phase by two clock cycles. The PCnet-PCI II controller will not assert DEVSEL for a PCI transaction that has an ad- dress parity error, when PERREN and SERREN are set to ONE. 19436A-13 FRAME CLK AD SERR C/ BE DEVSEL 1 2345 PAR PAR ADDR 1st DATA BE CMD PAR Figure 10. Address Parity Error Response |
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