ADM690–ADM695

REV. A

–7–

Table I. ADM691, ADM693, ADM695 Reset Pulse Width and Watchdog Timeout Selections

Watchdog Timeout Period

Reset Active Period

Immediately

OSC SEL

OSC IN

Normal

After Reset

ADM691/ADM693

ADM695

Low

External Clock Input

1024 CLKS

4096 CLKS

512 CLKS

2048 CLKS

Low

External Capacitor

260 ms

× C/47 pF 1.04 s × C/47 pF

130 ms

× C/47 pF

520 ms

× C/47 pF

Floating or High

Low

100 ms

1.6 s

50 ms

200 ms

Floating or High

Floating or High

1.6 s

1.6 s

50 ms

200 ms

NOTE

With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal

The watchdog timeout period is fixed at 1.6 seconds, and the

reset pulse width is fixed at 50 ms on the ADM690/ADM692.

On the ADM694 the watchdog timeout period is also 1.6 sec-

onds but the reset pulse width is fixed at 200 ms. The ADM691/

ADM693/ADM695 allow these times to be adjusted as shown

in Table I. Figure 4 shows the various oscillator configurations

which can be used to adjust the reset pulse width and watchdog

timeout period.

The internal oscillator is enabled when OSC SEL is high or

floating. In this mode, OSC IN selects between the 1.6 second

and 100 ms watchdog timeout periods. With OSC IN connected

high or floating, the 1.6 second timeout period is selected; while

with it connected low, the 100 ms timeout period is selected. In

either case, immediately after a reset, the timeout period is 1.6

seconds. This gives the microprocessor time to reinitialize the

system. If OSC IN is low, then the 100 ms watchdog period be-

comes effective after the first transition of WDI. The software

should be written such that the I/O port driving WDI is left in

its power-up reset state until the initialization routines are com-

pleted and the microprocessor is able to toggle WDI at the mini-

mum watchdog timeout period of 70 ms.

Watchdog Output (WDO)

The Watchdog Output WDO (ADM691/ADM693/ADM695)

provides a status output which goes low if the watchdog timer

“times out” and remains low until set high by the next transition

below the reset threshold.

OSC IN

OSC SEL

ADM691

ADM693

ADM695

CLOCK

0 TO 250kHz

8

7

Figure 4a. External Clock Source

OSC IN

OSC SEL

ADM691

ADM693

ADM695

8

7

C

OSC

Figure 4b. External Capacitor

OSC IN

OSC SEL

ADM691

ADM693

ADM695

8

7

NC

NC

Figure 4c. Internal Oscillator (1.6 Second Watchdog)

OSC IN

OSC SEL

ADM691

ADM693

ADM695

8

7

NC

Figure 4d. Internal Oscillator (100 ms Watchdog)