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AD9517-0ABCPZ датащи(PDF) 25 Page - Analog Devices

номер детали AD9517-0ABCPZ
подробное описание детали  12-Output Clock Generator with Integrated 2.8 GHz VCO
PDF  80 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9517-0ABCPZ датащи(HTML) 25 Page - Analog Devices

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Data Sheet
AD9517-0
Rev. E | Page 25 of 80
–100
–110
–120
–130
–140
–150
–160
10
100M
10M
1M
100k
10k
1k
100
FREQUENCY (Hz)
Figure 37. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4
–120
–160
–150
–140
–130
1k
100M
10M
1M
100k
10k
FREQUENCY (Hz)
Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO at 2.7 GHz;
PFD = 15.36 MHz; LBW = 110 kHz; LVPECL Output = 122.88 MHz
–90
–100
–110
–120
–130
–140
–150
–160
1k
100M
10M
1M
100k
10k
FREQUENCY (Hz)
Figure 39. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 2.8 GHz;
PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz
–120
–160
–150
–140
–130
1k
100M
10M
1M
100k
10k
FREQUENCY (Hz)
Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)
at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
1000
100
10
1
0.1
0.01
0.1
1
10
100
1000
JITTER FREQUENCY (kHz)
OC-48 OBJECTIVE MASK
AD9517
NOTE: 375UI MAX AT 10Hz OFFSET IS THE
MAXIMUM JITTER THAT CAN BE
GENERATED BY THE TEST EQUIPMENT.
FAILURE POINT IS GREATER THAN 375UI.
fOBJ
Figure 41. GR-253 Jitter Tolerance Plot



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