AD8111AST datasheet(21/29 Pages) AD

21 / 29 page

REV. A

AD8110/AD8111

–20–

From a circuit standpoint, this output crosstalk mechanism

looks like a transformer with a mutual inductance between the

windings that drives a load resistor. For low frequencies, the

magnitude of the crosstalk is given by:

Mxy

s R

=×

()

log

where Mxy is the mutual inductance of output x to output y,

and RL is the load resistance on the measured output. This

crosstalk mechanism can be minimized by keeping the mutual

inductance low and increasing RL. The mutual inductance can

be kept low by increasing the spacing of the conductors and

minimizing their parallel length.

PCB Layout

Extreme care must be exercised to minimize additional crosstalk

generated by the system circuit board(s). The areas that must be

carefully detailed are grounding, shielding, signal routing, and

supply bypassing.

The packaging of the AD8110/AD8111 is designed to help keep

the crosstalk to a minimum. Each input is separated from each

other input by an analog ground pin. All of these AGNDs should

be directly connected to the ground plane of the circuit board.

These ground pins provide shielding, low impedance return

paths and physical separation for the inputs. All of these help to

reduce crosstalk.

Each output is separated from its two neighboring outputs by an

analog ground pin in addition to an analog supply pin of one

polarity or the other. Each of these analog supply pins provides

power to the output stages of only the two nearest outputs. These

supply pins and analog grounds provide shielding, physical

separation and a low impedance supply for the outputs. Individual

bypassing of each of these supply pins with a 0.01

µF chip capaci-

tor directly to the ground plane minimizes high frequency output

crosstalk via the mechanism of sharing common impedances.

Each output also has an on-chip compensation capacitor that is

individually tied to the nearby analog ground pins AGND00

through AGND07. This technique reduces crosstalk by prevent-

ing the currents that flow in these paths from sharing a common

impedance on the IC and in the package pins. These AGNDxx

signals should all be directly connected to the ground plane.

The input and output signals will have minimum crosstalk if

they are located between ground planes on layers above and

below, and separated by ground in between. Vias should be

located as close to the IC as possible to carry the inputs and

outputs to the inner layer. The only place the input and output

signals surface is at the input termination resistors and the out-

put series back termination resistors. These signals should also

be separated, to the extent possible, as soon as they emerge from

the IC package.

Evaluation Board

A four-layer evaluation board is available for the AD8110/AD8111.

The exact same board and external components are used for

each device. The only difference is the device itself, which offers

a selection of a gain of unity or gain of two through the analog

channels. This board has been carefully laid out and tested to

demonstrate the specified high-speed performance of the device.

Figure 9 shows the schematic of the evaluation board. Figure 10

shows the component side silk-screen. The layouts of the board’s

four layers are given in:

Component Layer—Figure 11

Signal Routing Layer—Figure 12

Power Layer—Figure 13

Bottom Layer—Figure 14

The evaluation board package includes the following:

• Fully populated board with BNC-type connectors.

• Windows® based software for controlling the board from a PC

via the printer port.

• Custom cable to connect evaluation board to PC.

• Disk containing Gerber files of board layout.

Optimized for video applications, all signal inputs and outputs

are terminated with 75

Ω resistors. Stripline techniques are used

to achieve a characteristic impedance on the signal input and

output lines also of 75

Ω. Figure 8 shows a cross-section of one

of the input or output tracks along with the arrangement of the

PCB layers. It should be noted that unused regions of the four

layers are filled up with ground planes. As a result, the input

and output traces, in addition to having controlled impedances,

are well shielded.

w = 0.008"

(0.2mm)

a = 0.008"

(0.2mm)

b = 0.024"

(0.6mm)

h = 0.011325"

(0.288mm)

t = 0.00135" (0.0343mm)

TOP LAYER

SIGNAL LAYER

POWER LAYER

BOTTOM LAYER

Figure 8. Cross Section of Input and Output Traces

The board has 24 BNC type connectors: 16 inputs and 8 outputs.

The connectors are arranged in a crescent around the device. As

can be seen from Figure 12, this results in all 16 input signal

traces and all eight signal output traces having the same length.

This is useful in tests such as All-Hostile Crosstalk where the

phase relationship and delay between signals needs to be

maintained from input to output.

Windows is a registered trademark of Microsoft Corporation

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