AD652KP datasheet(18/28 Pages) AD

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AD652

Rev. C | Page 18 of 28

This can be shown in equation form, where fC is the AD654

output frequency and fOUT is the AD652 output frequency:

MHz

f =

⎟

⎠

⎞

⎜

⎝

⎛

OUT

()()⎟

⎟

⎠

⎞

⎜

⎝

⎛

MHz

OUT

fOUT = V1 × V2 × 5 kHz/V2

The scope photo in Figure 24 shows V1 and V2 (top two traces)

and the output of the F-V (bottom trace).

VOUT

Figure 24. Multiplier Waveforms

SINGLE-LINE MULTIPLEXED DATA TRANSMISSION

It is often necessary to measure several different signals and

relay the information to some remote location using a mini-

mum amount of cable. Multiple AD652 SVFC devices may be

used with a multiphase clock to combine these measurements

for serial transmission and demultiplexing. Figure 25 shows a

block diagram of a single-line multiplexed data transmission

system with high noise immunity. Figure 26, Figure 27, and

Figure 30 show the SVFC multiplexer, a representative means of

data transmission, and an SVFC demultiplexer respectively.

Multiplexer

Figure 30 shows the SVFC multiplexer. The clock inputs for the

several SVFC channels are generated by a TIM9904A 4-phase

clock driver, and the frequency outputs are combined by

strapping all the frequency output pins together (a wire OR

connection). The one-shot in the AD652 sets the pulse width of

the frequency output pulses to be slightly shorter than one

quarter of the clock period. Synchronization is achieved by

applying one of the four available phases to a fixed TTL one-

shot (’121) and combining the output with external transistor.

The width of this sync pulse is shorter than the width of the

frequency output pulses to facilitate decoding the signal. The

RC lag network on the input of the one-shot provides a slight

delay between the rising edge of the clock and the sync pulse in

order to match the 150 ns delay of the AD652 between the

rising edge of the clock and the output pulse.

Transmitter

The multiplex signal can be transmitted in any manner suitable

to the task at hand. A pulse transformer or an opto-isolator can

provide galvanic isolation; extremely high voltage isolation or

transmission through severe RF environments can be accomp-

lished with a fiber optic link; telemetry can be achieved with a

radio link. The circuit shown in Figure 27 uses an EIA RS-422

standard for digital data transmission over a balanced line.

Figure 24 shows the waveforms of the four clock phases and the

multiplex output signal. Note that the sync pulse is present

every clock cycle, but the data pulses are no more frequent than

every other clock cycle since the maximum output frequency

from the SVFC is half the clock frequency. The clock frequency

used in this circuit is 819.2 kHz, which provides more than

16 bits of resolution if 100 ms gate time is allowed for counting

pulses of the decoded output frequencies.

AD652

VIN1

AD652

VIN2

AD652

VIN3

ONE

SHOT

φ1

φ2

φ3

φ4

CLK

GENERATOR

SVFC MULTIPLEXER

(SEE FIGURE 26)

AD652

VOUT1

AD652

VOUT2

AD652

VOUT3

SVFC

DEMUX

SVFC DEMULTIPLEXER

(SEE FIGURE 30)

DEMULTIPLEXER FREQUENCY TO

VOLTAGE CONVERSION

(SEE FIGURE 31)

TRANSMISSION

LINK

TRANSMISSION

LINK

(SEE FIGURE 27)

Figure 25. Single-Line Multiplexed Data Transmission Block Diagram

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